ADCMP572/ADCMP573 Data Sheet
Rev. B | Page 10 of 14
V
CCO
is the signal return for the output stage and V
CCO
pins
should of course be connected to a supply plane for maximum
performance.
OPTIMIZING HIGH SPEED PERFORMANCE
As with any high speed comparator, proper design and layout
techniques are essential to obtaining the specified performance.
Stray capacitance, inductance, inductive power and ground
impedances, or other layout issues can severely limit performance
and often cause oscillation. Discontinuities along input and
output transmission lines can severely limit the specified pulse
width dispersion performance.
For applications working in a 50 Ω environment, input and
output matching has a significant impact on data dependent (or
deterministic) jitter (DJ) and on pulse width dispersion
performance. The ADCMP572/ADCMP573 comparators
provide internal 50 Ω termination resistors for both the V
P
and
V
N
inputs, and the ADCMP572 provides 50 Ω back terminated
outputs. The return side for each input termination is pinned
out separately with the V
TP
and V
TN
pins, respectively. If a 50 Ω
termination is desired at one or both of the V
P
/V
N
inputs, then
the V
TP
and V
TN
pins can be connected (or disconnected) to
(from) the desired termination potential as required. The
termination potential should be carefully bypassed using high
quality bypass capacitors as discussed earlier to prevent undesired
aberrations on the input signal due to parasitic inductance in
the circuit board layout. If a 50 Ω input termination is not
desired, either one or both of the V
TP
/V
TN
termination pins can
be left disconnected. In this case, the pins should be left floating
with no external pull-downs or bypassing capacitors.
When leaving an input termination disconnected, the internal
resistor acts as a small stub on the input transmission path and
can cause problems for very high speed inputs. Reflections
should then be expected from the comparator inputs because
they no longer provide matched impedance to the input path
leading to the device. In this case, it is important to back match
the drive source impedance to the input transmission path to
minimize multiple reflections. For applications in which the
comparator is very close to the driving signal source, the source
impedance should be minimized. High source impedance in
combination with parasitic input capacitance of the comparator
might cause an undesirable degradation in bandwidth at the
input, therefore degrading the overall response. Although the
ADCMP572/ADCMP573 comparators have been designed to
minimize input capacitance, some parasitic capacitance is
inevitable. It is therefore recommended that the drive source
impedance be no more than 50 Ω for best high speed performance.
COMPARATOR PROPAGATION
DELAY DISPERSION
The ADCMP572/ADCMP573 comparators are designed to
reduce propagation delay dispersion over a wide input overdrive
range of 5 mV to 500 mV. Propagation delay dispersion is variation
in the propagation delay that results from a change in the degree of
overdrive or slew rate (how far or how fast the input signal
exceeds the switching threshold).
Propagation delay dispersion is a specification that becomes
important in high speed, time-critical applications such as data
communication, automatic test and measurement, instrumenta-
tion, and event driven applications such as pulse spectroscopy,
nuclear instrumentation, and medical imaging. Dispersion is
defined as the variation in propagation delay as the input over-
drive conditions vary (Figure 17 and Figure 18). For the
ADCMP572/ADCMP573, dispersion is typically <15 ps
because the overdrive varies from 10 mV to 500 mV, and the
input slew rate varies from 2 V/ns to 10 V/ns. This specification
applies for both positive and negative signals since the
ADCMP572/ADCMP573 has substantially equal delays for
either positive going or negative going inputs.
Q/Q OUTPUT
INPUT VOLTAGE
500mV OVERDRIVE
10mV OVERDRIVE
DISPERSION
V
N
± V
OS
04409-0-027
Figure 17. Propagation Delay—Overdrive Dispersion
Q/Q OUTPUT
INPUT VOLTAGE
10V/ns
1V/ns
DISPERSION
V
N
± V
OS
04409-0-028
Figure 18. Propagation Delay—Slew Rate Dispersion
Data Sheet ADCMP572/ADCMP573
Rev. B | Page 11 of 14
COMPARATOR HYSTERESIS
The addition of hysteresis to a comparator is often desirable in a
noisy environment or when the differential input amplitudes are
relatively small or slow moving, but excessive hysteresis has a
cost in degraded accuracy and slew-induced timing shifts. The
transfer function for a comparator with hysteresis is shown in
Figure 19. If the input voltage approaches the threshold (0.0 V
in this example) from the negative direction, the comparator
switches from low to high when the input crosses + V
H
/2. The
new switching threshold becomes −V
H
/2. The comparator
remains in the high state until the threshold −V
H
/2 is crossed
from the positive direction. In this manner, noise centered on
0.0 V input does not cause the comparator to switch states
unless it exceeds the region bounded by ±V
H
/2.
OUTPUT
INPUT
0
V
OL
V
OH
+V
H
2
–V
H
2
04409-005
Figure 19. Comparator Hysteresis Transfer Function
The customary technique for introducing hysteresis into a
comparator uses positive feedback from the output back to the
input. A limitation of this approach is that the amount of
hysteresis varies with the output logic levels, resulting in
hysteresis that can be load dependent and is not symmetrical
about the threshold. The external feedback network can also
introduce significant parasitics, which reduce high speed
performance and can even induce oscillation in some cases.
The ADCMP572/ADCMP573 comparators offer a program-
mable hysteresis feature that can significantly improve the
accuracy and stability of the desired hysteresis. By connecting
an external pull-down resistor from the HYS pin to GND, a
variable amount of hysteresis can be applied. Leaving the HYS
pin disconnected disables the feature, and hysteresis is then less
than 1 mV as specified. The maximum hysteresis that can be
applied using this method is approximately ±25 mV with the
pin grounded. Figure 20 illustrates the amount of hysteresis
applied as a function of external resistor value. The advantages of
applying hysteresis in this manner are improved accuracy, stability,
and reduced component count. An external bypass capacitor is
not recommended on the HYS pin because it would likely degrade
the jitter performance of the device. The hysteresis pin could also
be driven by a CMOS DAC. It is biased to approximately 250 mV
and has an internal series resistance of 600 Ω.
0
10
20
30
40
50
60
HYSTERESIS (mV)
2301 456
R
HYS
(k)
04409-043
Figure 20. Hysteresis vs. R
HYS
Control Resistor
MINIMUM INPUT SLEW RATE REQUIREMENTS
As with all high speed comparators, a minimum slew rate
requirement must be met to ensure that the device does not
oscillate as the input signal crosses the threshold. This oscillation is
due in part to the high input bandwidth of the comparator and
the feedback parasitics inherent in the package. A minimum
slew rate of 50 V/μs should ensure clean output transitions from
the ADCMP572/ADCMP573 comparators.
The slew rate may be too slow for other reasons. The extremely
high bandwidth of these devices means that broadband noise
can be a significant factor when input slew rates are low. There
will be at least 120 μV of thermal noise generated over the full
comparator bandwidth by two 50 Ω terminations at room
temperature. With a slew rate of only 50 V/μs the input will be
inside this noise band for over 2 ps, rendering the comparator’s
jitter performance of 200 fs moot. Raising the slew rate of the
input signal and/or reducing the bandwidth over which this
resistance is seen at the input can greatly reduce jitter.
ADCMP572/ADCMP573 Data Sheet
Rev. B | Page 12 of 14
TYPICAL APPLICATION CIRCUITS
Q
3.3V
50 50
ADCMP572
Q
V
IN
V
P
V
TP
V
TN
V
N
LATCH
INPUTS
04409-029
V
CCI
V
CCO
Figure 21. Zero-Crossing Detector with 3.3 V CML Outputs
Q
5050
Q
V
P
V
N
V
P
V
TP
V
TN
V
N
LATCH
INPUTS
04409-030
V
CCI
= 5.2V
ADCMP572
V
CCO
Figure 22. LVDS to 50 Ω Back Terminated RSPECL Receiver
50 50
+
Q
Q
V
IN
V
TH
LATCH
INPUTS
GND = –1V
04409-031
V
CCI
= 3.3V
V
CCO
= 3.3V 3.3V
ADCMP572
Figure 23. Comparator with ±1 V Input Range and 3.3 V CML Outputs
5050
Q
Q
V
IN
V
TH
LATCH
INPUTS
04409-032
V
CCI
= 5.2V
V
CCO
= 3.3V/5.2V 3.3V/5.2V
ADCMP572
Figure 24. Comparator with 0 V to 3 V Input Range and
3.3 V or 5.2 V Positive CML Outputs
LATCH
INPUTS
04409-034
V
CCI
V
CCO
= 3.3V 5V
75
50
50
100
100
ADCMP572
Figure 25. Interfacing 3.3 V CML to a 50 Ω
Ground Terminated Instrument
V
P
V
N
V
CCO
= 3.3V V
CCO
V
CCO
0
4409-035
V
CCI
ADCMP572
50
1.35k
50
Figure 26. Disabling the ADCMP572 Latch Feature
V
P
V
N
500
04409-048
V
CCI
= 5.2V = V
CCO
V
TT
= 3.2V
V
CCO
ADCMP573
50 50
Figure 27. Disabling the ADCMP573 Latch Feature
HYS
V
CCO
V
CCO
04409-036
V
CCI
ADCMP572
50 50
0 TO 5k
Figure 28. Adding Hysteresis Using the HYS Control Pin

ADCMP573BCPZ-R2

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog Comparators Ultrafast 3.3V SGL-Supply
Lifecycle:
New from this manufacturer.
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