Data Sheet ADCMP572/ADCMP573
Rev. B | Page 9 of 14
APPLICATIONS INFORMATION
POWER/GROUND LAYOUT AND BYPASSING
The ADCMP572/ADCMP573 comparators are very high speed
SiGe devices. Consequently, it is essential to use proper high speed
design techniques to achieve the specified performance. Of critical
importance is the use of low impedance supply planes, particularly
the output supply plane (V
CCO
) and the ground plane (GND).
Individual supply planes are recommended as part of a multilayer
board. Providing the lowest inductance return path for switching
currents ensures the best possible performance in the target
application.
It is important to adequately bypass the input and output supplies.
A 1 μF electrolytic bypass capacitor should be placed within
several inches of each power supply pin to ground. In addition,
multiple high quality 0.01 μF bypass capacitors should be placed
as close as possible to each of the V
CCI
and V
CCO
supply pins and
should be connected to the GND plane with redundant vias. High
frequency bypass capacitors should be carefully selected for
minimum inductance and ESR. Parasitic layout inductance should
be avoided to maximize the effectiveness of the bypass at high
frequencies.
If the input and output supplies are connected separately such
that V
CCI
≠ V
CCO
, care should be taken to bypass each of these
supplies separately to the GND plane. A bypass capacitor should
not be connected between them. It is recommended that the
GND plane separate the V
CCI
and V
CCO
planes when the circuit
board layout is designed to minimize coupling between the two
supplies and to take advantage of the additional bypass capaci-
tance from each respective supply to the ground plane. This
enhances the performance when split input/output supplies are
used. If the input and output supplies are connected together for
single-supply operation such that V
CCI
= V
CCO
, coupling between
the two supplies is unavoidable; however, every effort should be
made to keep the supply plane adjacent to the GND plane to
maximize the additional bypass capacitance this arrangement
provides.
CML/RSPECL OUTPUT STAGE
Specified propagation delay dispersion performance can be
achieved only by using proper transmission line terminations.
The outputs of the ADCMP572 are designed to directly drive
400 mV into 50 Ω cable, microstrip, or strip line transmission
lines properly terminated to the V
CCO
supply plane. The CML
output stage is shown in the simplified schematic diagram of
Figure 15. The outputs are each back terminated with 50 Ω for
best transmission line matching. The RSPECL outputs of the
ADCMP573 are illustrated in Figure 16 and should be terminated
to V
CCO
− 2 V. As an alternative, evenin equivalent termination
networks can be used in either case if the direct termination
voltage is not readily available. If high speed output signals must
be routed more than a centimeter, microstrip or strip line
techniques are essential to ensure proper transition times and to
prevent output ringing and pulse width dependent propagation
delay dispersion. For the most timing critical applications where
transmission line reflections pose the greatest risk to performance,
the ADCMP572 provides the best match to 50 Ω output
transmission paths.
Q
16mA
50
Q
04409-037
V
CCO
GND
Figure 15. Simplified Schematic Diagram of
the ADCMP572 CML Output Stage
04409-038
V
CCO
GND
Q
Q
Figure 16. Simplified Schematic Diagram of
the ADCMP573 RSPECL Output Stage
USING/DISABLING THE LATCH FEATURE
The latch inputs (LE/
LE
) are active low for latch mode and are
internally terminated with 50 Ω resistors to Pin 8. This pin
corresponds to and is internally connected to the V
CCO
supply
for the CML-compatible ADCMP572. With the aid of these
resistors, the ADCMP572 latch function can be disabled by
connecting the
LE
pin to GND with an external pull-down
resistor and leaving the LE pin unconnected. To avoid excessive
power dissipation, the resistor should be 750 Ω when V
CCO
=
3.3 V, and 1.2 kΩ when V
CCO
= 5.2 V. In the PECL-compatible
ADCMP573, the V
TT
pin should be connected externally to the
PECL termination supply at V
CCO
– 2 V. The latch can then be
disabled by connecting the LE pin to V
CCO
with an external
500 Ω resistor and leaving the
LE
pin disconnected. In this case,
the resistor value does not depend on the V
CCO
supply voltage.
