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ADCMP573BCPZ-R2

P1-P3P4-P6P7-P9P10-P12P13-P14
ADCMP572/ADCMP573 Data Sheet
Rev. B | Page 4 of 14
Parameter Symbol Conditions Min Typ Max Unit
AC PERFORMANCE
Propagation Delay t
PD
V
CCI
= 3.3 V, V
OD
= 200 mV 150 Ps
V
CCI
= 3.3 V, V
OD
= 20 mV 165 Ps
V
CCI
= 5.2 V, V
OD
= 200 mV 145 Ps
Propagation Delay Tempco ∆t
PD
/d
T
0.5 ps/°C
Prop Delay Skew—Rising Transition
to Falling Transition
V
OD
= 200 mV, 5 V/ns 10 Ps
Overdrive Dispersion 50 mV < V
OD
< 0.2 V, 5 V/ns 15 Ps
10 mV < V
OD
< 0.2 V, 5 V/ns 15 Ps
Slew Rate Dispersion 2 V/ns to 10 V/ns, 250 mV OD 15 Ps
Pulse Width Dispersion 100 ps to 5 ns, 250 mV OD 5 Ps
10% – 90% Duty Cycle Dispersion V
CCI
= 3.3 V, 1 V/ns, 250 mV OD 5 Ps
V
CCI
= 5.2 V, 1 V/ns, 250 mV OD 10
Common-Mode Dispersion V
OD
= 0.2 V, 0.0 V < V
CM
< 2.9 V 5 ps/V
Equivalent Input Bandwidth
1
BW
EQ
0.0 V to 250 mV input
t
R
= t
F
= 17 ps, 20/80
8.0 GHz
Toggle Rate >50% Output Swing 12.5 Gbps
Deterministic Jitter DJ
V
OD
= 200 mV, 5 V/ns,
PRBS
31
− 1 NRZ, 4 Gbps
10 Ps
V
OD
= 200 mV, 5 V/ns,
PRBS
31
− 1 NRZ, 10 Gbps
20 Ps
RMS Random Jitter RJ V
OD
= 200 mV, 5 V/ns, 1.25 GHz 0.2 Ps
Minimum Pulse Width PW
MIN
∆t
PD
/∆PW < 5 ps, 200 mV OD 100 Ps
PW
MIN
∆t
PD
/∆PW < 10 ps, 200 mV OD 80 Ps
Rise Time t
R
20/80 35 Ps
Fall Time t
F
20/80 35 Ps
POWER SUPPLY
Input Supply Voltage Range V
CCI
3.1 5.4 V
Output Supply Voltage Range V
CCO
3.1 5.4 V
Positive Supply Differential V
CCI
− V
CCO
−0.2 +2.3 V
ADCMP572 (CML)
Positive Supply Current I
VCCI
+ I
VCCO
V
CCI
= 3.3 V, V
CCO
= 3.3 V,
terminate 50 Ω to V
CCO
44 52 mA
V
CCI
= 5.2 V, V
CCO
= 5.2 V,
terminate 50 Ω to V
CCO
44 52
Device Power Dissipation P
D
V
CCI
= 3.3 V, V
CCO
= 3.3 V,
terminate 50 Ω to V
CCO
140 165 mW
V
CCI
= 5.2 V, V
CCO
= 5.2 V,
terminate 50 Ω to V
CCO
230 265
ADCMP573 (RSPECL)
Positive Supply Current I
VCCI
+ I
VCCO
V
CCI
= 3.3 V, V
CCO
= 3.3 V,
50 Ω to V
CCO
− 2 V
62 80 mA
V
CCI
= 5.2 V, V
CCO
= 5.2 V,
50 Ω to V
CCO
– 2 V
64 80
Device Power Dissipation P
D
V
CCI
= 3.3 V, V
CCO
= 3.3 V,
50 Ω to V
CCO
− 2 V
110 160 mW
V
CCI
= 5.2 V, V
CCO
= 5.2 V,
50 Ω to V
CCO
− 2 V
146 230
1
Equivalent input bandwidth assumes a simple first-order response and is calculated with the following formula: BW
EQ
= 0.22/√(tr
COMP
2
−tr
IN
2
), where tr
IN
is the 20/80
transition time of a quasi-Gaussian signal applied to the comparator input, and tr
COMP
is the effective transition time digitized by the comparator.
Data Sheet ADCMP572/ADCMP573
Rev. B | Page 5 of 14
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
SUPPLY VOLTAGE
Input Supply Voltage
(V
CCI
to GND)
−0.5 V to +6.0 V
Output Supply Voltage
(V
CCO
to GND)
−0.5 V to +6.0 V
Positive Supply Differential
(V
CCI
− V
CCO
)
−0.5 V to +3.5 V
INPUT VOLTAGE
Input Voltage −0.5 V to V
CCI
+ 0.5 V
Differential Input Voltage ±(V
CCI
+ 0.5 V)
Input Voltage, Latch Enable −0.5 V to V
CCO
+ 0.5 V
HYSTERESIS CONTROL PIN
Applied Voltage (HYS to GND) −0.5 V to +1.5 V
Maximum Input/Output Current ±1 mA
OUTPUT CURRENT
ADCMP572 (CML) ±20 mA
ADCMP573 (RSPECL) −35 mA
TEMPERATURE
Operating Temperature, Ambient −40°C to +125°C
Operating Temperature, Junction +150°C
Storage Temperature Range −65°C to +150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL CONSIDERATIONS
The ADCMP572/ADCMP573 LFCSP 16-lead package has a θ
JA
(junction-to-ambient thermal resistance) of 70°C/W in still air.
ESD CAUTION
ADCMP572/ADCMP573 Data Sheet
Rev. B | Page 6 of 14
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
04409-026
LE
Q
12
11
10
1
3
4
9
2
6
5
7
8
16
15
14
13
NOTES
1. LEAVE EPAD FLOATING UNLESS IMPROVED THERMAL OR MECHANICAL
STABILITY IS DESIRED, IN WHICH CASE SOLDER IT TO THE APPLICATION BOARD.
V
TP
V
P
V
N
V
TN
V
CCO
GND
HYS
GND
V
CCI
Q
V
CCO
V
CCI
LE
V
CCO
/V
TT
ADCMP572
ADCMP573
TOP VIEW
Figure 2. ADCMP572/ADCMP573 Pin Configuration
Table 3. Pin Function Descriptions
Pin
No. Mnemonic Description
1 V
TP
Termination Resistor Return Pin for V
P
Input.
2 V
P
Noninverting Analog Input.
3 V
N
Inverting Analog Input.
4 V
TN
Termination Resistor Return Pin for V
N
Input.
5, 16 V
CCI
Positive Supply Voltage for Input Stage.
6
LE
Latch Enable Input Pin, Inverting Side.
In compare mode (LE
= low), the output tracks changes at the input of the comparator.
In latch mode (LE
= high), the output reflects the input state just prior to the comparator’s being placed into latch
mode. LE
must be driven in complement with LE.
7 LE
Latch Enable Input Pin, Noninverting Side.
In compare mode (LE = high), the output tracks changes at the input of the comparator.
In latch mode (LE = low), the output reflects the input state just prior to the comparator’s being placed into latch
mode. LE must be driven in complement with LE
.
8 V
CCO
/V
TT
Termination Return Pin for the LE/LE
Input Pins.
For the ADCMP572 (CML output stage), this pin is internally connected to and also should be externally connected
to the positive V
CCO
supply.
For the ADCMP573 (RSPECL output stage), this pin should normally be connected to the V
CCO
– 2 V termination
potential.
9, 12 V
CCO
Positive Supply Voltage for the CML/RSPECL Output Stage.
13, 15 GND Ground.
10
Q
Inverting Output. Q is at logic low if the analog voltage at the noninverting input, V
P
, is greater than the analog
voltage at the inverting input, V
N
, provided the comparator is in compare mode. See the LE/LE descriptions (Pins 6
and 7) for more information.
11 Q
Noninverting Output. Q is at logic high if the analog voltage at the noninverting input V
P
is greater than the analog
voltage at the inverting input, V
N
, provided the comparator is in compare mode.
See the LE/LE
descriptions (Pins 6 and 7) for more information.
14 HYS
Hysteresis Control Pin. Leave this pin disconnected for zero hysteresis. Connect to GND with a suitably sized
resistor to add the desired amount of hysteresis. Refer to Figure 7 for proper sizing of R
HYS
hysteresis control
resistor.
Isolated
Heat Sink
The metallic back surface of the package is not electrically connected to any part of the circuit, and it can be left
floating for best electrical isolation between the package handle and the substrate of the die. However, it can be
soldered to the application board if improved thermal and/or mechanical stability is desired. Exposed metal at
package corners is connected to the heat sink paddle.
EPAD
Exposed Pad. Leave EPAD floating unless improved thermal or mechanical stability is desired, in which case solder
it to the application board.
P1-P3P4-P6P7-P9P10-P12P13-P14

ADCMP573BCPZ-R2

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Buy ADCMP573BCPZ-R2
Manufacturer:
Analog Devices Inc.
Description:
Analog Comparators Ultrafast 3.3V SGL-Supply
Lifecycle:
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