MTA18ASF2G72PF1Z-2G6V21AB Datasheet MTA18ASF2G72PF1Z-2G6V21AB | P7-P9

Pin Descriptions

The pin description table below is a comprehensive list of all possible pins for DDR4

UDIMM, RDIMM, SODIMM, and LRDIMM modules. All pins listed may not be suppor-

ted on the module defined in this data sheet. See functional block diagram specific to

this module to review all pins utilized on this module.

Table 5: Pin Descriptions

Symbol Type Description

Ax Input Address inputs: Provide the row address for ACTIVATE commands and the column

address for READ/WRITE commands to select one location out of the memory array in

the respective bank. (A10/AP, A12/BC_n, WE_n/A14, CAS_n/A15, and RAS_n/A16 have

additional functions; see individual entries in this table). The address inputs also pro-

vide the op-code during the MODE REGISTER SET command. A17 is only defined for

x4 SDRAM configuration.

A10/AP Input Auto precharge: A10 is sampled during READ and WRITE commands to determine

whether auto precharge should be performed to the accessed bank after a READ or

WRITE operation (HIGH = Auto precharge; LOW = No auto precharge). A10 is sampled

during a PRECHARGE command to determine whether the PRECHARGE applies to one

bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the

bank is selected by the bank group and bank addresses.

A12/BC_n Input Burst chop: A12/BC_n is sampled during READ and WRITE commands to determine if

burst chop (on-the-fly) will be performed. (HIGH = No burst chop; LOW = Burst-chop-

ped). See the Command Truth Table in DDR4 component data sheet for more informa-

tion.

ACT_n Input Command input: ACT_n defines the activation command being entered along with

CS_n. The input into RAS_n/A16, CAS_n/A15, and WE_n/A14 will be considered as row

address A16, A15, and A14. See the Command Truth Table in DDR4 component data

sheet for more information.

BAx Input Bank address inputs: Define to which bank an ACTIVATE, READ, WRITE, or PRE-

CHARGE command is being applied. Also determines which mode register is to be ac-

cessed during a MODE REGISTER SET command.

BGx Input Bank group address inputs: Define to which bank group a REFRESH, ACTIVATE,

READ, WRITE, or PRECHARGE command is being applied. Also determines which

mode register is to be accessed during a MODE REGISTER SET command. BG[1:0] are

used in the x4 and x8 configurations. x16-based SDRAMs only have BG0.

C0, C1, C2

(RDIMM/LRDIMM

only)

Input Chip ID: These inputs are used only when devices are stacked, that is, 2H, 4H, and 8H

stacks for x4 and x8 configurations using though-silicon vias (TSVs). These pins are not

used in the x16 configuration. Some DDR4 modules support a traditional DDP pack-

age, which use CS1_n, CKE1, and ODT1 to control the second die. For all other stack

configurations, such as a 4H or 8H, it is assumed to be a single-load (master/slave)-

type configuration where C0, C1, and C2 are used as chip ID selects in conjunction

with a single CS_n, CKE, and ODT. Chip ID is considered part of the command code.

CKx_t

CKx_c

Input Clock: Differential clock inputs. All address, command, and control input signals are

sampled on the crossing of the positive edge of CK_t and the negative edge of CK_c.

16GB (x72, ECC, SR) 288-Pin DDR4 Nonvolatile RDIMM

Pin Descriptions

CCMTD-1725822587-10375

asf18c2gx72pf1z.pdf - Rev. C 7/17 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 5: Pin Descriptions (Continued)

Symbol Type Description

CKEx Input Clock enable: CKE HIGH activates, and CKE LOW deactivates, the internal clock sig-

nals, device input buffers, and output drivers. Taking CKE LOW provides PRECHARGE

POWER-DOWN and SELF REFRESH operations (all banks idle), or active power-down

(row active in any bank). CKE is asynchronous for self refresh exit. After V

REFCA

has be-

come stable during the power-on and initialization sequence, it must be maintained

during all operations (including SELF REFRESH). CKE must be held HIGH throughout

read and write accesses. Input buffers (excluding CK_t, CK_c, ODT, RESET_n, and CKE)

are disabled during power-down. Input buffers (excluding CKE and RESET_n) are disa-

bled during self refresh.

CSx_n Input Chip select: All commands are masked when CS_n is registered HIGH. CS_n provides

external rank selection on systems with multiple ranks. CS_n is considered part of the

command code. CS2_n and CS3_n are not used on UDIMMs.

ODTx Input On-die termination: ODT (registered HIGH) enables termination resistance internal

to the DDR4 SDRAM. When ODT is enabled, on-die termination (R

) is applied only to

each DQ, DQS_t, DQS_c, DM_n/DBI_n/TDQS_t, and TDQS_c signal for x4 and x8 config-

urations (when the TDQS function is enabled via the mode register). For the x16 con-

figuration, R

is applied to each DQ, DQSU_t, DQSU_c, DQSL_t, DQSL_c, UDM_n, and

LDM_n signal. The ODT pin will be ignored if the mode registers are programmed to

disable R

PARITY Input Parity for command and address: This function can be enabled or disabled via the

mode register. When enabled in MR5, then DRAM calculates Parity with ACT_n,

RAS_n/A16, CAS_n/A15, WE_n/A14, BG[1:0], BA[1:0], A[16:0]. Input parity should be

maintained at the rising edge of the clock and at the same time with command and

address with CS_n LOW.

RAS_n/A16

CAS_n/A15

WE_n/A14

Input Command inputs: RAS_n/A16, CAS_n/A15, and WE_n/A14 (along with CS_n) define

the command and/or address being entered. Those pins have multifunction. For exam-

ple, for activation with ACT_n LOW, these are addresses like A16, A15, and A14, but

for a non-activation command with ACT_n HIGH, these are command pins for READ,

WRITE, and other commands defined in the command truth table.

RESET_n CMOS Input Active LOW asynchronous reset: Reset is active when RESET_n is LOW; inactive

when RESET_n is HIGH. RESET_n must be HIGH during normal operation. RESET_n is

blocked when NVDIMM is armed.

SAx Input

Serial address inputs: Used to configure the temperature sensor/SPD EEPROM ad-

dress range on the I

C bus.

SCL Input

Serial clock for temperature sensor/SPD EEPROM: Used to synchronize communi-

cation to and from the temperature sensor/SPD EEPROM on the I

C bus.

DQx, CBx I/O Data input/output and Check Bit input/output : Bidirectional data bus. DQ repre-

sents DQ[3:0], DQ[7:0], and DQ[15:0] for the x4, x8, and x16 configurations, respec-

tively. If cyclic redundancy checksum (CRC) is enabled via the mode register, then CRC

code is added at the end of the data burst. Either one or all of DQ0, DQ1, DQ2, or

DQ3 is/are used for monitoring the internal V

REF

level during test via mode register

setting MR[4] A[4] = HIGH; training times change when enabled.

16GB (x72, ECC, SR) 288-Pin DDR4 Nonvolatile RDIMM

Pin Descriptions

CCMTD-1725822587-10375

asf18c2gx72pf1z.pdf - Rev. C 7/17 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 5: Pin Descriptions (Continued)

Symbol Type Description

DM_n/DBI_n/

TDQS_t(DMU_n,DBI

U_n),(DML_n/

DBIl_n)

I/O Input Data Mask and Data Bus Inversion: DM_n is an input mask signal for write

data. Input data is masked when DM_n is sampled LOW coincident with that input da-

ta during a write access. DM_n is sampled on both edges of DQS. DM is mux’ed with

DBI function by mode register A10, A11, A12 setting in MR5. For x8 device, the func-

tion of DM or TDQS is enabled by mode register A11 setting in MR1. DBI_n is an in-

put/output identifying whether to store/output the true or inverted data. If DBI_n is

LOW, the data will be stored/output after inversion inside the DDR4 SDRAM and not

inverted if DBI_n is HIGH. TDQS is only supported in x8 SDRAM configurations. TDQS

is not valid for UDIMMs.

DQS_t

DQS_c

DQSU_t

DQSU_c

DQSL_t

DQSL_c

I/O Data strobe: Output with read data, input with write data. Edge-aligned with read

data, centered-aligned with WRITE data. For x16 configurations, DQSL corresponds to

the data on DQ[7:0]; DQSU corresponds to the data on DQ[15:8]. For the x4 and x8

configurations, DQS corresponds to the data on DQ[3:0] and DQ[7:0] respectively.

DDR4 SDRAM support a differential data strobe only and do not support a single-

ended data strobe.

ALERT_n Output Alert output: Possesses multifunctions such as CRC error flag and command and ad-

dress parity error flag as output signal. If there is a CRC error, then ALERT_n goes LOW

for the period time interval and returns HIGH. If there is error in command address

parity check, then ALERT_n goes LOW until on-going DRAM internal recovery transac-

tion is complete. During connectivity test mode this pin functions as an input. Using

this signal or not is dependent on the system. If not connected as signal, ALERT_n pin

must be connected to V

on DIMM.

EVENT_n Output Temperature event: The EVENT_n pin is asserted by the temperature sensor when

critical temperature thresholds have been exceeded. This pin has no function (NF) on

modules without temperature sensors.

SAVE_n Input (open

drain)

Force Save: Active LOW, open-drain input pulled up to 2.5V through a 2K resistor.

Commands the Micron NVDIMM to switch its internal MUXs and copy the data in the

SDRAM to internal NAND Flash. The SDRAM must be placed in self refresh mode be-

fore asserting this pin to ensure that no data is lost during this operation.

TDQS_t

TDQS_c

(x8 DRAM based

RDIMM only)

Output Termination data strobe: TDQS_t and TDQS_c are not valid for UDIMMs. When ena-

bled via the mode register, the SDRAM enable the same R

termination resistance on

TDQS_t and TDQS_c that is applied to DQS_t and DQS_c. When the TDQS function is

disabled via the mode register, the DM/TDQS_t pin provides the data mask (DM) func-

tion, and the TDQS_c pin is not used. The TDQS function must be disabled in the

mode register for both the x4 and x16 configurations. The DM function is supported

only in x8 and x16 configurations. DM, DBI, and TDQS are a shared pin and are ena-

bled/disabled by mode register settings. For further information about TDQS, refer to

DDR4 DRAM data sheet.

Supply Module Power supply: 1.21V (typical)

Supply DRAM activating power supply: 2.5V –0.125V / +0.250V

REFCA

Supply Reference voltage for control, command, and address pins.

Supply Ground.

Supply Power supply for termination of address, command, and control, V

/2.

DDSPD

Supply Power supply used to power the I

C bus used for SPD.

16GB (x72, ECC, SR) 288-Pin DDR4 Nonvolatile RDIMM

Pin Descriptions

CCMTD-1725822587-10375

asf18c2gx72pf1z.pdf - Rev. C 7/17 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P26

MTA18ASF2G72PF1Z-2G6V21AB

Mfr. #:

Buy MTA18ASF2G72PF1Z-2G6V21AB

Manufacturer:

Micron

Description:

Memory Modules DDR4 NVDIMM 16GB NVRDIMM-N NA

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet

MTA18ASF2G72PF1Z-2G6V21AB