OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

NCP3218AMNR2G

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P35
ADP3212A, NCP3218A
http://onsemi.com
28
The most effective way to reduce switching loss is to use
lower gate capacitance devices.
The conduction loss of the main MOSFET is given by the
following equation:
P
C(MF)
+ D
ƪ
ǒ
I
O
n
MF
Ǔ
2
)
1
12
ǒ
n I
R
n
MF
Ǔ
2
ƫ
R
DS(MF)
(eq. 16)
where R
DS(MF)
is the on resistance of the MOSFET.
Typically, a user wants the highest speed (low C
ISS
)
device for a main MOSFET, but such a device usually has
higher on resistance. Therefore, the user must select a device
that meets the total power dissipation (about 0.8 W to 1.0 W
for an 8−lead SOIC) when combining the switching and
conduction losses.
For example, an IRF7821 device can be selected as the
main MOSFET (four in total; that is, n
MF
= 4), with
approximately
C
ISS
= 1010 pF (maximum) and R
DS(MF)
= 18 mW
(maximum at T
J
= 120°C), and an IR7832 device can be
selected as the synchronous MOSFET (four in total; that is,
n
SF
= 4), with
R
DS(SF)
= 6.7 mW (maximum at T
J
= 120°C). Solving for the
power dissipation per MOSFET at I
O
= 40 A and I
R
= 9.0 A
yields 630 mW for each synchronous MOSFET and
590 mW for each main MOSFET. A third synchronous
MOSFET is an option to further increase the conversion
efficiency and reduce thermal stress.
Finally, consider the power dissipation in the driver for
each phase. This is best described in terms of the Q
G
for the
MOSFETs and is given by the following equation:
P
DRV
+
ƪ
f
SW
2 n
(n
MF
Q
GMF
) n
SF
Q
GSF
) ) I
CC
ƫ
VCC
(eq. 17)
where Q
GMF
is the total gate charge for each main
MOSFET, and Q
GSF
is the total gate charge for each
synchronous MOSFET.
The previous equation also shows the standby dissipation
(I
CC
times the VCC) of the driver.
Ramp Resistor Selection
The ramp resistor (R
R
) is used to set the size of the internal
PWM ramp. The value of this resistor is chosen to provide
the best combination of thermal balance, stability, and
transient response. Use the following expression to
determine a starting value:
R
R
+
A
R
L
3 A
D
R
DS
C
R
(eq. 18)
R
R
+
0.5 360 nH
3 5 5.2 mW 5pF
+ 462 kW
where:
A
R
is the internal ramp amplifier gain.
A
D
is the current balancing amplifier gain.
R
DS
is the total low−side MOSFET on resistance.
C
R
is the internal ramp capacitor value.
Another consideration in the selection of R
R
is the size of
the internal ramp voltage (see Equation 19). For stability and
noise immunity, keep the ramp size larger than 0.5 V. Taking
this into consideration, the value of R
R
in this example is
selected as 280 kW.
The internal ramp voltage magnitude can be calculated as
follows:
V
R
+
A
R
(1 * D) V
VID
R
R
C
R
f
SW
(eq. 19)
V
R
+
0.5 (1 * 0.061) 1.150 V
462 kW 5pF 280 kHz
+ 0.83 V
The size of the internal ramp can be increased or
decreased. If it is increased, stability and transient response
improves but thermal balance degrades. Conversely, if the
ramp size is decreased, thermal balance improves but
stability and transient response degrade. In the denominator
of Equation 18, the factor of 3 sets the minimum ramp size
that produces an optimal combination of good stability,
transient response, and thermal balance.
Current Limit Setpoint
To select the current limit setpoint, the resistor value for
R
CLIM
must be determined. The current limit threshold for
the APD3212A/NCP3218A is set with R
CLIM
. R
CLIM
can be
found using the following equation:
R
LIM
+
I
LIM
R
O
60 mA
(eq. 20)
where:
R
LIM
is the current limit resistor.
R
O
is the output load line.
I
LIM
is the current limit setpoint.
When the APD3212A/NCP3218A is configured for 3
phase operation, the equation above is used to set the current
limit. When the APD3212A/NCP3218A switches from 3
phase to 1 phase operation by PSI
or DPRSLP signal, the
current is single phase is one third of the current limit in 3
phase.
When the APD3212A/NCP3218A is configured for 2
phase operation, the equation above is used to set the current
limit. When the APD3212A/NCP3218A switches from 2
phase to 1 phase operation by PSI
or DPRSLP signal, the
current is single phase is one half of the current limit in 2
phase.
When the APD3212A/NCP3218A is configured for 1
phase operation, the equation above is used to set the current
limit.
Current Monitor
The APD3212A/NCP3218A has output current monitor.
The IMON pin sources a current proportional to the total
inductor current. A resistor, R
MON
, from IMON to FBRTN
sets the gain of the output current monitor. A 0.1 mF is placed
in parallel with R
MON
to filter the inductor current ripple and
ADP3212A, NCP3218A
http://onsemi.com
29
high frequency load transients. Since the IMON pin is
connected directly to the CPU, it is clamped to prevent it
from going above 1.15 V.
The IMON pin current is equal to the R
LIM
times a fixed
gain of 4. R
MON
can be found using the following equation:
R
MON
+
1.15 V R
LIM
4 R
O
I
FS
(eq. 21)
where:
R
MON
is the current monitor resistor. R
MON
is connected
from IMON pin to FBRTN.
R
LIM
is the current limit resistor.
R
O
is the output load line resistance.
I
FS
is the output current when the voltage on IMON is at full
scale.
Feedback Loop Compensation Design
Optimized compensation of the APD3212A/NCP3218A
allows the best possible response of the regulator’s output to
a load change. The basis for determining the optimum
compensation is to make the regulator and output
decoupling appear as an output impedance that is entirely
resistive over the widest possible frequency range, including
dc, and that is equal to the droop resistance (R
O
). With the
resistive output impedance, the output voltage droops in
proportion with the load current at any load current slew
rate, ensuring the optimal position and allowing the
minimization of the output decoupling.
With the multimode feedback structure of the
APD3212A/NCP3218A, it is necessary to set the feedback
compensation so that the converter’s output impedance
works in parallel with the output decoupling. In addition, it
is necessary to compensate for the several poles and zeros
created by the output inductor and decoupling capacitors
(output filter).
A Type III compensator on the voltage feedback is
adequate for proper compensation of the output filter.
Figure 31 shows the Type III amplifier used in the
APD3212A/NCP3218A. Figure 32 shows the locations of
the two poles and two zeros created by this amplifier.
COMP
FB
REFERENCE
VOLTAGE
VOLTAGE ERROR
AMPLIFIER
ADP3212
OUTPUT
VOLTAGE
Figure 31. Voltage Error Amplifier
R
A
C
A
C
FB
C
B
R
FB
Figure 32. Poles and Zeros of Voltage Error Amplifier
0 dB
Gain
Frequency
−20 dB/dec
−20 dB/dec
f
Z1
f
P0
f
P1
f
Z2
The following equations give the locations of the poles
and zeros shown in Figure 32:
f
Z1
+
1
2p C
A
R
A
(eq. 22)
f
Z2
+
1
2p C
FB
R
FB
(eq. 23)
f
P0
+
1
2p (C
A
) C
B
) R
FB
(eq. 24)
f
P1
+
C
A
) C
B
2p R
A
C
B
C
A
(eq. 25)
The expressions that follow compute the time constants
for the poles and zeros in the system and are intended to yield
an optimal starting point for the design; some adjustments
may be necessary to account for PCB and component
parasitic effects (see the Tuning Procedure for 12 section):
R
E
+ n R
O
) A
D
R
DS
)
R
L
V
RT
V
VID
)
(eq. 26)
2 L (1 * (n D)) V
RT
n C
X
R
O
V
VID
T
A
+ C
X
(R
O
* RȀ) )
L
X
R
O
R
O
* RȀ
R
X
(eq. 27)
T
B
+ (R
X
) RȀ*R
O
) C
X
(eq. 28)
T
C
+
V
RT
ǒ
L *
A
D
R
DS
2 f
SW
Ǔ
V
VID
R
E
(eq. 29)
T
D
+
C
X
C
Z
R
O
2
C
X
(R
O
* RȀ) ) C
Z
R
O
(eq. 30)
where:
R′ is the PCB resistance from the bulk capacitors to the
ceramics and is approximately 0.4 mW (assuming an 8−layer
motherboard).
R
DS
is the total low−side MOSFET for on resistance per
phase.
A
D
is 5.
V
RT
is 1.25 V.
L
X
is 150 pH for the six Panasonic SP capacitors.
ADP3212A, NCP3218A
http://onsemi.com
30
The compensation values can be calculated as follows:
C
A
+
n R
O
T
A
R
E
R
B
(eq. 31)
R
A
+
T
C
C
A
(eq. 32)
C
B
+
T
B
R
B
(eq. 33)
C
FB
+
T
D
R
A
(eq. 34)
The standard values for these components are subject to
the tuning procedure described in the Tuning Procedure for
12 section.
C
IN
Selection and Input Current di/dt Reduction
In continuous inductor−current mode, the source current
of the high−side MOSFET is approximately a square wave
with a duty ratio equal to n × V
OUT
/V
IN
and an amplitude
that is one−n
th
of the maximum output current. To prevent
large voltage transients, use a low ESR input capacitor sized
for the maximum rms current. The maximum rms capacitor
current occurs at the lowest input voltage and is given by:
I
CRMS
+ D I
O
1
n D
* 1
Ǹ
(eq. 35)
I
CRMS
+ 0.18 40 A
1
2 0.18
* 1
Ǹ
+ 9.6 A
where I
O
is the output current.
In a typical notebook system, the battery rail decoupling
is achieved by using MLC capacitors or a mixture of MLC
capacitors and bulk capacitors. In this example, the input
capacitor bank is formed by eight pieces of 10 mF, 25 V MLC
capacitors, with a ripple current rating of about 1.5 A each.
RC Snubber
It is important in any buck topology to use a
resistor−capacitor snubber across the low side power
MOSFET. The RC snubber dampens ringing on the switch
node when the high side MOSFET turns on. The switch node
ringing could cause EMI system failures and increased
stress on the power components and controller. The RC
snubber should be placed as close as possible to the low side
MOSFET. Typical values for the resistor range from 1 W to
10 W. Typical values for the capacitor range from 330 pF to
4.7 nF. The exact value of the RC snubber depends on the
PCB layout and MOSFET selection. Some fine tuning must
be done to find the best values. The equation below is used
to find the starting values for the RC subber.
R
Snubber
+
1
2 p f
Ringing
C
OSS
(eq. 36)
C
Snubber
+
1
p f
Ringing
R
Snubber
(eq. 37)
P
Snubber
+ C
Snubber
V
Input
2
f
Switching
(eq. 38)
Where R
Snubber
is the snubber resistor.
C
Snubber
is the snubber capacitor.
f
Rininging
is the frequency of the ringing on the switch node
when the high side MOSFET turns on.
C
OSS
is the low side MOSFET output capacitance at V
Input
.
This is taken from the low side MOSFET data sheet.
V
input
is the input voltage.
f
Switching
is the switching frequency.
P
Snubber
is the power dissipated in R
Snubber
.
Selecting Thermal Monitor Components
To monitor the temperature of a single−point hot spot, set
R
TTSET1
equal to the NTC thermistor’s resistance at the alarm
temperature. For example, if the alarm temperature for VRTT
is 100°C and a Vishey thermistor (NTHS−0603N011003J)
with a resistance of 100 kW at 25°C, or 6.8 kW at 100°C, is
used, the user can set R
TTSET1
equal to 6.8 kW (the R
TH1
at
100°C).
Figure 33. Single−Point Thermal Monitoring
TTSNS
ADP3212
VCC
R
5 V
VRTT
R
R
TH1
C
TT
R
TTSET1
To monitor the temperature of multiple−point hot spots,
use the configuration shown in Figure 34. If any of the
monitored hot spots reaches the alarm temperature, the
VRTT signal is asserted. The following calculation sets the
alarm temperature:
R
TTSET1
+
1ń2 )
V
FD
V
REF
1ń2 *
V
FD
V
REF
R
TH1AlarmTemperature
(eq. 39)
where V
FD
is the forward drop voltage of the parallel diode.
Because the forward current is very small, the forward
drop voltage is very low, that is, less than 100 mV. Assuming
the same conditions used for the single−point thermal
monitoring example—that is, an alarm temperature of
100°C and use of an NTHS−0603N011003J Vishay
thermistor—solving Equation 39 gives a R
TTSET
of 7.37 kW,
and the closest standard resistor is 7.32 kW (1%).
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P35

NCP3218AMNR2G

Mfr. #:
Buy NCP3218AMNR2G
Manufacturer:
ON Semiconductor
Description:
Switching Controllers 3 PHASE BUCK CONTROLLER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet