ADP3212A, NCP3218A
http://onsemi.com
7
ELECTRICAL CHARACTERISTICS
V
CC
= PV
CC
= 5.0 V, FBRTN = PGND = GND = 0 V, H = 5.0 V, L = 0 V, EN = VARFREQ = H, DPRSLP = L, PSI = 1.05 V,
V
VID
= V
DAC
= 1.2000 V, T
A
= 40°C to 100°C, unless otherwise noted. (Note 1) Current entering a pin (sink current) has a positive sign.
Parameter UnitsMaxTypMinConditionsSymbol
CURRENT MONITOR
Current Gain Accuracy
I
MON
/I
LIM
Measured from I
LIM
to I
MON
I
LIM
= 20 mA
I
LIM
= 10 mA
I
LIM
= 5 mA
3.7
3.6
3.5
4.0
4.0
4.0
4.3
4.4
4.5
I
MON
Clamp Voltage V
MAXMON
Relative to FBRTN, ILIMP = 30 mA
1.0 1.16 V
PULSE WIDTH MODULATOR CLOCK OSCILLATOR
RT Voltage
V
RT
VARFREQ = high, R
T
= 125 kW,
V
VID
= 1.5000 V
VARFREQ = low
See also V
RT
(V
VID
) formula
1.125
0.9
1.25
1.0
1.375
1.1
V
PWM Clock Frequency Range
(Note 2)
f
CLK
Operation of interest 0.3 3.0 MHz
PWM Clock Frequency f
CLK
T
A
= +25°C, V
VID
= 1.2000 V
R
T
= 72 kW
R
T
= 120 kW
R
T
= 180 kW
900
700
300
1200
800
400
1500
900
500
kHz
RAMP GENERATOR
RAMP Voltage
V
RAMP
EN = high, I
RAMP
= 60 mA
EN = low
0.9 1.0
V
IN
1.1 V
RAMP Current Range (Note 2) I
RAMP
EN = high
EN = low, RAMP = 19 V
1.0
1.0
100
+1.0
mA
PWM COMPARATOR
PWM Comparator Offset (Note 2)
V
OSRPM
V
RAMP
V
COMP
±3.0 mV
RPM COMPARATOR
RPM Current
I
RPM
V
VID
= 1.2 V, R
T
= 215 kW
See also I
RPM
(R
T
) formula
5.5
mA
RPM Comparator Offset (Note 2) V
OSRPM
V
COMP
(1 + V
RPMTH
) ±3.0 mV
EPWM CLOCK SYNC
Trigger Threshold (Note 2)
Relative to COMP sampled T
CLK
time
earlier
3phase configuration
2phase configuration
1phase configuration
350
400
450
mV
TRDET
Trigger Threshold (Note 2) Relative to COMP sampled T
CLK
time
earlier
3phase configuration
2phase configuration
1phase configuration
450
500
600
mV
TRDET Low Voltage (Note 2) V
LTRDET
Logic low, I
TRDETsink
= 4 mA 30 300 mV
TRDET Leakage Current I
HTRDET
Logic high, V
TRDET
= VCC 3.0
mA
SWITCH AMPLIFIER
SW Common Mode Range
(Note 2)
V
SW(X)CM
Operation of interest for current sensing 600 +200 mV
SWFB Input Resistance R
SW(X)
SW
X
= 0 V, SWFB = 0 V 20 35 50
kW
ZERO CURRENT SWITCHING COMPARATOR
SW ZCS Threshold
V
DCM(SW1)
DCM mode, DPRSLP = 3.3 V 3.0 mV
Masked OffTime t
OFFMSKD
Measured from DRVH1 neg edge to
DRVH1 pos edge at operation max
frequency
600 ns
1. All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).
2. Guaranteed by design or bench characterization, not production tested.
3. Based on bench characterization data.
4. Timing is referenced to the 90% and 10% points, unless otherwise noted.
ADP3212A, NCP3218A
http://onsemi.com
8
ELECTRICAL CHARACTERISTICS
V
CC
= PV
CC
= 5.0 V, FBRTN = PGND = GND = 0 V, H = 5.0 V, L = 0 V, EN = VARFREQ = H, DPRSLP = L, PSI = 1.05 V,
V
VID
= V
DAC
= 1.2000 V, T
A
= 40°C to 100°C, unless otherwise noted. (Note 1) Current entering a pin (sink current) has a positive sign.
Parameter UnitsMaxTypMinConditionsSymbol
SYSTEM I/O BUFFERS
VID[6:0], DPRSLP, PSI
INPUTS
Input Voltage Refers to driving signal level
Logic low
Logic high
0.7
0.3
V
Input Current V = 0.2 V, VID[6:0], DPRSLP
(active pulldown to GND)
PSI
(active pullup to VCC)
1.0
2.0
mA
VID Delay Time (Note 2) Any VID edge to FB change 10% 200 ns
VARFREQ
Input Voltage
Refers to driving signal level
Logic low
Logic high
4.0
0.7
V
Input Current 1.0
mA
EN INPUT
Input Voltage
Refers to driving signal level
Logic low
Logic high 1.7
0.5
V
Input Current EN = L or EN = H (static)
0.8 V < EN < 1.6 V (during transition)
10
70
nA
mA
PH1, PH0 INPUTS
Input Voltage
Refers to driving signal level
Logic low
Logic high
2.0
0.5
V
Input Current 1.0
mA
CLKEN OUTPUT
Output Low Voltage
Logic low, I
sink
= 4 mA 60 200 mV
Output High, Leakage Current Logic high, V
CLKEN
= VCC 0.1
mA
PWM3, OD3 OUTPUTS
Output Voltage
Logic low, I
SINK
= 400 mA
Logic high, I
SOURCE
= 400 mA
4.0
10
5.0
500 mV
V
THERMAL MONITORING and PROTECTION
TTSNS Voltage Range (Note 2)
0 5.0 V
TTSNS Threshold VCC = 5.0 V, TTSNS is falling 2.45 2.5 2.55 V
TTSNS Hysteresis 50 95 mV
TTSNS Bias Current TTSNS = 2.6 V 2.0 2.0
mA
VRTT Output Voltage V
VRTT
Logic low, I
VRTT(SINK)
= 400 mA
Logic high, I
VRTT(SOURCE)
= 400 mA
4.5
10
5.0
500 mV
V
SUPPLY
Supply Voltage Range
V
CC
4.5 5.5 V
Supply Current EN = high
EN = 0 V
7
10
10
50
mA
mA
VCC OK Threshold V
CCOK
VCC is rising 4.4 4.5 V
VCC UVLO Threshold V
CCUVLO
VCC is falling 4.0 4.15 V
VCC Hysteresis (Note 2) 250 mV
HIGHSIDE MOSFET DRIVER
Pullup Resistance, Sourcing
Current (Note 3)
BST = PVCC 1.25 3.3
W
1. All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).
2. Guaranteed by design or bench characterization, not production tested.
3. Based on bench characterization data.
4. Timing is referenced to the 90% and 10% points, unless otherwise noted.
ADP3212A, NCP3218A
http://onsemi.com
9
ELECTRICAL CHARACTERISTICS
V
CC
= PV
CC
= 5.0 V, FBRTN = PGND = GND = 0 V, H = 5.0 V, L = 0 V, EN = VARFREQ = H, DPRSLP = L, PSI = 1.05 V,
V
VID
= V
DAC
= 1.2000 V, T
A
= 40°C to 100°C, unless otherwise noted. (Note 1) Current entering a pin (sink current) has a positive sign.
Parameter UnitsMaxTypMinConditionsSymbol
HIGHSIDE MOSFET DRIVER
Pulldown Resistance, Sinking
Current (Note 3)
BST = PVCC 0.8 2.0
W
Transition Times tr
DRVH
tf
DRVH
BST = PVCC, C
L
= 3 nF, Figure 2
BST = PVCC, C
L
= 3 nF, Figure 2
15
13
35
31
ns
Dead Delay Times tpdh
DRVH
BST = PVCC, Figure 2
T = 10°C to 100°C
T = 40°C to 100°C
28 32 36
50
ns
BST Quiescent Current EN = L (Shutdown)
EN = H, no switching
1.0
200
10
mA
LOWSIDE MOSFET DRIVER
Pullup Resistance, Sourcing
Current (Note 3)
0.88 2.8
W
Pulldown Resistance, Sinking
Current (Note 3)
0.65 1.7
W
Transition Times tr
DRVL
tf
DRVL
C
L
= 3 nF, Figure 2
C
L
= 3 nF, Figure 2
15
14
35
35
ns
Propagation Delay Times tpdh
DRVL
C
L
= 3 nF, Figure 2
T = 10°C to 100°C
T = 40°C to 100°C
11
12
30
40
ns
SW Transition Timeout t
TOSW
DRVH = L, SW = 2.5 V
T = 10°C to 100°C
T = 40°C to 100°C
85
85
250
250
300
450
ns
SW Off Threshold V
OFFSW
1.6 V
PVCC Quiescent Current EN = L (Shutdown)
EN = H, no switching
1.0
170
10
mA
BOOTSTRAP RECTIFIER SWITCH
On Resistance (Note 3)
EN = L or EN = H and DRVL = H 5.0 7.0 12
W
1. All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).
2. Guaranteed by design or bench characterization, not production tested.
3. Based on bench characterization data.
4. Timing is referenced to the 90% and 10% points, unless otherwise noted.
Figure 2. Timing Diagram (Note 4)
IN
DRVH
(WITH RESPECT TO SW)
DRVL
SW
1.0 V
tf
DRVH
V
TH
V
TH
tpdh
DRVL
tpdl
DRVH
tr
DRVL
tpdh
DRVH
tr
DRVH
tf
DRVL
tpdl
DRVL

NCP3218AMNR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Switching Controllers 3 PHASE BUCK CONTROLLER
Lifecycle:
New from this manufacturer.
Delivery:
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