NCP3218AMNR2G Datasheet NCP3218AMNR2G, ADP3212AMNR2G | P31-P33

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Figure 34. Multiple−Point Thermal Monitoring

ADP3212

TTSNS

−

VCC

5 V

VRTT

TH1

TH2

TTSET1

TTSET2

TH3

TTSET3

The number of hot spots monitored is not limited. The

alarm temperature of each hot spot can be individually set by

using different values for R

TTSET1

, R

TTSET2

, ... R

TTSETn

Tuning Procedure for APD3212A/NCP3218A

Set Up and Test the Circuit

1. Build a circuit based on the compensation values

computed from the design spreadsheet.

2. Connect a dc load to the circuit.

3. Turn on the APD3212A/NCP3218A and verify

that it operates properly.

4. Check for jitter with no load and full load

conditions.

Set the DC Load Line

1. Measure the output voltage with no load (V

)

and verify that this voltage is within the specified

tolerance range.

2. Measure the output voltage with a full load when

the device is cold (V

FLCOLD

). Allow the board to

run for ~10 minutes with a full load and then

measure the output when the device is hot

FLHOT

). If the difference between the two

measured voltages is more than a few millivolts,

adjust R

CS2

using Equation 40.

CS2(NEW)

+ R

CS2(OLD)

* V

FLCOLD

* V

FLHOT

(eq. 40)

3. Repeat Step 2 until no adjustment of R

CS2

needed.

4. Compare the output voltage with no load to that

with a full load using 5 A steps. Compute the load

line slope for each change and then find the

average to determine the overall load line slope

OMEAS

5. If the difference between R

OMEAS

and R

is more

than 0.05 mW, use the following equation to adjust

the R

values:

PH(NEW)

+ R

PH(OLD)

OMEAS

(eq. 41)

6. Repeat Steps 4 and 5 until no adjustment of R

needed. Once this is achieved, do not change R

CS1

, R

CS2

, or R

for the rest of the procedure.

7. Measure the output ripple with no load and with a

full load with scope, making sure both are within

the specifications.

Set the AC Load Line

1. Remove the dc load from the circuit and connect a

dynamic load.

2. Connect the scope to the output voltage and set it

to dc coupling mode with a time scale of

100 ms/div.

3. Set the dynamic load for a transient step of about

40 A at 1 kHz with 50% duty cycle.

4. Measure the output waveform (note that use of a

dc offset on the scope may be necessary to see the

waveform). Try to use a vertical scale of

100 mV/div or finer.

5. The resulting waveform will be similar to that

shown in Figure 35. Use the horizontal cursors to

measure V

ACDRP

and V

DCDRP

, as shown in

Figure 35. Do not measure the undershoot or

overshoot that occurs immediately after the step.

Figure 35. AC Load Line Waveform

DCDRP

ACDRP

6. If the difference between V

ACDRP

and V

DCDRP

more than a couple of millivolts, use Equation 42

to adjust C

. It may be necessary to try several

parallel values to obtain an adequate one because

there are limited standard capacitor values

available (it is a good idea to have locations for

two capacitors in the layout for this reason).

CS(NEW)

+ C

CS(OLD)

ACDRP

DCDRP

(eq. 42)

7. Repeat Steps 5 and 6 until no adjustment of C

needed. Once this is achieved, do not change C

for the rest of the procedure.

8. Set the dynamic load step to its maximum step size

(but do not use a step size that is larger than

needed) and verify that the output waveform is

square, meaning V

ACDRP

and V

DCDRP

are equal.

9. Ensure that the load step slew rate and the

powerup slew rate are set to ~150 A/ms to

250 A/ms (for example, a load step of 50 A should

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take 200 ns to 300 ns) with no overshoot. Some

dynamic loads have an excessive overshoot at

powerup if a minimum current is incorrectly set

(this is an issue if a VTT tool is in use).

Set the Initial Transient

1. With the dynamic load set at its maximum step

size, expand the scope time scale to 2 ms/div to

5 ms/div. This results in a waveform that may have

two overshoots and one minor undershoot before

achieving the final desired value after V

DROOP

(see Figure 36).

Figure 36. Transient Setting Waveform, Load Step

TRAN1

DROOP

TRAN2

2. If both overshoots are larger than desired, try the

following adjustments in the order shown.

a. Increase the resistance of the ramp resistor

RAMP

) by 25%.

b. For V

TRAN1

, increase C

or increase the switching

frequency.

c. For V

TRAN2

, increase R

by 25% and decrease C

by 25%.

If these adjustments do not change the response, it is

because the system is limited by the output

decoupling. Check the output response and the

switching nodes each time a change is made to

ensure that the output decoupling is stable.

3. For load release (see Figure 37), if V

TRANREL

larger than the value specified by IMVP−6.5, a

greater percentage of output capacitance is needed.

Either increase the capacitance directly or decrease

the inductor values. (If inductors are changed,

however, it will be necessary to redesign the

circuit using the information from the spreadsheet

and to repeat all tuning guide procedures).

Figure 37. Transient Setting Waveform, Load Release

TRANREL

DROOP

Layout and Component Placement

The following guidelines are recommended for optimal

performance of a switching regulator in a PC system.

General Recommendations

1. For best results, use a PCB of four or more layers.

This should provide the needed versatility for

control circuitry interconnections with optimal

placement; power planes for ground, input, and

output; and wide interconnection traces in the rest

of the power delivery current paths. Keep in mind

that each square unit of 1 oz copper trace has a

resistance of ~0.53 mW at room temperature.

2. When high currents must be routed between PCB

layers, vias should be used liberally to create

several parallel current paths so that the resistance

and inductance introduced by these current paths is

minimized and the via current rating is not

exceeded.

3. If critical signal lines (including the output voltage

sense lines of the APD3212A/NCP3218A) must

cross through power circuitry, it is best if a signal

ground plane can be interposed between those

signal lines and the traces of the power circuitry.

This serves as a shield to minimize noise injection

into the signals at the expense of increasing signal

ground noise.

4. An analog ground plane should be used around

and under the APD3212A/NCP3218A for

referencing the components associated with the

controller. This plane should be tied to the nearest

ground of the output decoupling capacitor, but

should not be tied to any other power circuitry to

prevent power currents from flowing into the

plane.

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5. The components around the

APD3212A/NCP3218A should be located close to

the controller with short traces. The most

important traces to keep short and away from other

traces are those to the FB and CSSUM pins. Refer

to Figure 30 for more details on the layout for the

CSSUM node.

6. The output capacitors should be connected as close

as possible to the load (or connector) that receives

the power (for example, a microprocessor core). If

the load is distributed, the capacitors should also

be distributed and generally placed in greater

proportion where the load is more dynamic.

7. Avoid crossing signal lines over the switching

power path loop, as described in the Power

Circuitry section.

8. Connect a 1 mF decoupling ceramic capacitor from

VCC to GND. Place this capacitor as close as

possible to the controller. Connect a 4.7 mF

decoupling ceramic capacitor from PVCC to

PGND. Place capacitor as close as possible to the

controller.

Power Circuitry

1. The switching power path on the PCB should be

routed to encompass the shortest possible length to

minimize radiated switching noise energy (that is,

EMI) and conduction losses in the board. Failure

to take proper precautions often results in EMI

problems for the entire PC system as well as

noise−related operational problems in the

power−converter control circuitry. The switching

power path is the loop formed by the current path

through the input capacitors and the power

MOSFETs, including all interconnecting PCB

traces and planes. The use of short, wide

interconnection traces is especially critical in this

path for two reasons: it minimizes the inductance

in the switching loop, which can cause high energy

ringing, and it accommodates the high current

demand with minimal voltage loss.

2. When a power−dissipating component (for

example, a power MOSFET) is soldered to a PCB,

the liberal use of vias, both directly on the

mounting pad and immediately surrounding it, is

recommended. Two important reasons for this are

improved current rating through the vias and

improved thermal performance from vias extended

to the opposite side of the PCB, where a plane can

more readily transfer heat to the surrounding air.

To achieve optimal thermal dissipation, mirror the

pad configurations used to heat sink the MOSFETs

on the opposite side of the PCB. In addition,

improvements in thermal performance can be

obtained using the largest possible pad area.

3. The output power path should also be routed to

encompass a short distance. The output power path

is formed by the current path through the inductor,

the output capacitors, and the load.

4. For best EMI containment, a solid power ground

plane should be used as one of the inner layers and

extended under all power components.

Signal Circuitry

1. The output voltage is sensed and regulated

between the FB and FBRTN pins, and the traces of

these pins should be connected to the signal

ground of the load. To avoid differential mode

noise pickup in the sensed signal, the loop area

should be as small as possible. Therefore, the FB

and FBRTN traces should be routed adjacent to

each other, atop the power ground plane, and back

to the controller.

2. The feedback traces from the switch nodes should

be connected as close as possible to the inductor.

The CSREF signal should be Kelvin connected to

the center point of the copper bar, which is the

CORE

common node for the inductors of all the

phases.

3. On the back of the APD3212A/NCP3218A

package, there is a metal pad that can be used to

heat sink the device. Therefore, running vias under

the APD3212A/NCP3218A is not recommended

because the metal pad may cause shorting between

vias.

ORDERING INFORMATION

Device Number* Temperature Range Package Package Option Shipping

†

ADP3212AMNR2G −40°C to 100°C 48−Lead Frame Chip Scale Pkg [QFN_VQ]

7x7 mm, 0.5 mm pitch

CP−48−1 2500 / Tape & Reel

NCP3218AMNR2G −40°C to 100°C 48−Lead Frame Chip Scale Pkg [QFN_VQ]

6x6 mm, 0.4 mm pitch

CP−48−1 2500 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specification Brochure, BRD8011/D.

*The “G’’ suffix indicates Pb−Free package.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P35

NCP3218AMNR2G

Mfr. #:

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Manufacturer:

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Description:

Switching Controllers 3 PHASE BUCK CONTROLLER

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