AMIS−49587
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Table 7. AMIS−49587 QFN PIN FUNCTION DESCRIPTION
Pin
No.
DescriptionTypeI/OPin Name
37 TX_ENB Out D, 5V Safe TX enable bar (open drain)
42 TX_OUT Out A Transmitter output
43 ALC_IN In A Automatic level control input
46 VDDA P 3.3 V analog supply
47 VSSA P Analog ground
48 RX_OUT Out A Output of receiver low noise operational amplifier
49 RX_IN In A Positive input of receiver low noise operational amplifier
51 REF_OUT Out A Reference output for stabilization
2, 3, ..
50, 52
NC Pins 2, 3, 4, 5, 12, 13, 14, 15, 19,23, 25, 26, 27, 28, 30, 34, 38, 39, 40,
42, 44, 45, 50, 52 are not connected. These pins need to be left open or
connected to the GND plane
P: Power pin
A: Analog pin
D: Digital pin
5V Safe: IO that support the presence of 5 V on bus line
Out: Output signal
In: Input signal
3.3 Detailed Pin Description
VDDA
VDDA is the positive analog supply pin. Nominal voltage is 3.3 V. A ceramic decoupling capacitor C
DA
= 100 nF $10% must
be placed between this pin and the VSSA. Connection path of this capacitance to the VSSA on the PCB should be kept as short
as possible in order to minimize the serial resistance.
REF_OUT
REF_OUT is the analog output pin which provides the voltage reference used by the A/D converter. This pin must be decoupled
to the analog ground by a 1 mF $10 percent ceramic capacitance C
DREF
. The connection path of this capacitor to the VSSA
on the PCB should be kept as short as possible in order to minimize the serial resistance.
VSSA
VSSA is the analog ground supply pin.
VDD
VDD is the 3.3 V digital supply pin. A ceramic decoupling capacitor C
DD
= 100 nF $10% must be placed between this pin
and the VSS. Connection path of this capacitance to the VSS on the PCB should be kept as short as possible in order to minimize
the serial resistance.
VSS
VSS is the digital ground supply pin.
AMIS−49587
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Figure 4. Recommended Layout of the Placement of Decoupling Capacitors for PLCC−28
8
9
10
7
6
5
12 13 14 17 18
22
21
20
19
23
24
25
3 2 27 26
VSSA
VDDA
28
1
1615
4
REF_OUT
C
C
DA
C
DD
GROUND
3,3V SUPPLY
VDD
VSS
11
DREF
RX_OUT
RX_OUT is the output analog pin of the receiver low noise input op−amp. This op−amp is in a negative feedback configuration.
RX_IN
RX_IN is the positive analog input pin of the receiver low noise input op−amp. Together with RX_OUT and REF_OUT, an
active high pass filter is realized. This filter removes the main frequency (50 or 60 Hz) from the received signal. The filter
characteristics are determined by external capacitors and resistors. A typical application schematic can be found in paragraph
50/60 Hz suppression filter.
M50Hz_IN
M50HZ_IN is the mains frequency analog input pin. The signal is used to detect the zero crossing of the 50 or 60 Hz sine wave.
This information is used, after filtering with the internal PLL, to synchronize frames with the mains frequency. In case of direct
connection to the mains it is advised to use a series resistor of 1 MW in combination with two external clamp diodes in order
to limit the current flowing through the internal protection diodes.
RX_DATA
RX_DATA is a 5 V compliant open drain output. An external pull−up resistor defines the logic high level as illustrated in
Figure 5. A typical value for the pull−up resistance “R” is 10 kW. The signal on this output depends on the status of the data
reception. If AMIS−49587 waits for configuration RX_DATA outputs a pulse train with a 10 Hz frequency. After
Synchronization Confirm Time out RX_DATA = 0. If AMIS−49587 is searching for synchronization RX_DATA = 1.
V
SSD
+5V
Output
R
Figure 5. Representation of 5V Safe Output
AMIS−49587
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TDO, TDI, TCK, TMS, and TRSTB
All these pins are part of the JTAG bus interface. The JTAG interface is used during production test of the IC and will not be
described here. Input pins (TDI, TCK, TMS, and TRSTB) contain internal pull−down resistance. TDO is an output. When not
used, the JTAG interface pins may be left floating.
TX_DATA/PRE_SLOT
TX_DATA/PRE_SLOT is the output for either the transmitting data (TX_DATA) or a synchronization signal with the
time−slots (PRE_SLOT). More information can be found in paragraph Local Port.
XIN
XIN is the analog input pin of the oscillator. It is connected to the interval oscillator inverter gain stage. The clock signal can
be created either internally with the external crystal and two capacitors or by connecting an external clock signal to XIN. For
the internal generation case, the two external capacitors and crystal are placed as shown in Figure 6. For the external clock
connection, the signal is connected to XIN and XOUT is left unused.
XTAL _IN XTAL_ OUT
C
X
V
SSA
C
X
R
X
24 MHz
Figure 6. Placement of the Capacitors and Crystal with Clock Signal Generated Internally
The crystal is a classical parallel resonance crystal of 24 MHz. The values of the capacitors C
X
are given by the manufacturer
of the crystal. A typical value is 30 pF. The crystal has to fulfill impedance characteristics specified in the AMIS−49587 data
sheet. As an oscillator is sensitive and precise, it is advised to put the crystal as close as possible on the board and to ground
the case.
XOUT
XOUT is the analog output pin of the oscillator. When the clock signal is provided from an external generator, this output must
be floating. When working with a crystal, this pin cannot be used directly as clock output because no additional loading is
allowed on the pin (limited voltage swing).
TXD
TXD is the digital output of the asynchronous serial communication (SCI) unit. Only half−duplex transmission is supported.
It is used to realize the communication between the AMIS−49587 and the application microcontroller. The TXD is an open
drain IO (5 V safe). External pull−up resistances (typically 10 kW) are necessary to generate the 5 V level. See Figure 5 for
the circuit schematic.
RXD
This is the digital input of the asynchronous SCI unit.
Only half−duplex transmission is supported. This pin supports a 5 V level. It is used to realize the communication between the
AMIS−49587 and the application microcontroller. RXD is a 5 V safe input.
T_REQ
T_REQ is the transmission request input of the Serial Communication Interface. When pulled low its initiate a local
communication from the application micro controller to AMIS−49587. T_REQ is a 5 V safe input.
BR1, BR0
BR0 and BR1 are digital input pins. They are used to select the baud rate (bits/second) of the Serial Communication Interface
unit. The rate is defined according to Table 28: BR1, BR0 Baud Rates. The values are taken into account after a reset, hardware
or software. Modification of the baud rate during function is not possible. BR0 and BR1 are 5 V safe.

AMIS49587C5871G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Network Controller & Processor ICs C587- NAF- AMIS49587
Lifecycle:
New from this manufacturer.
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