AD7899BRZ-1 Datasheet AD7899ARSZ-1, AD7899SRZ-1, AD7899ARSZ-2 | P13-P15

REV. A

AD7899

–12–

Standby Mode Operation

The AD7899 has a Standby Mode whereby the device can be

placed in a low current consumption mode (5 µA typ). The

AD7899 is placed in Standby by bringing the logic input STBY

low. The AD7899 can be powered again up for normal opera-

tion by bringing STBY logic high. The output data buffers are

still operational while the AD7899 is in Standby. This means

the user can still continue to access the conversion results while

the AD7899 is in standby. This feature can be used to reduce

the average power consumption in a system using low throughput

rates. To reduce the average power consumption, the AD7899

can be placed in standby at the end of each conversion sequence

and taken out of standby again prior to the start of the next

conversion sequence. The time it takes the AD7899 to come out

of standby is called the “wake up” time. This wake-up time will

limit the maximum throughput rate at which the AD7899 can

be operated when powering down between conversions. When

the AD7899 is used with the internal reference, the reference

capacitor will begin to discharge during standby. The voltage

remaining on the capacitor at wake-up time will depend upon

the standby time and hence affect the wake-up time. The mini-

mum wake-up time is typically 2 µs. The maximum wake-up

time will be when the AD7899 has been in standby long enough

for the reference capacitor to fully discharge. The wake-up time

in this case will typically be 15 ms. The AD7899 will wake up in

approximately 1 µs when using an external reference, regardless

of sleep time.

When operating the AD7899 in a Standby mode between con-

versions, the power savings can be significant. For example,

with a throughput rate of 10 kSPS and an external reference, the

AD7899 will be powered up for 4.2 µs out of every 100 µs (2 µs

for wake-up time and 2.2 µs for conversion time). Therefore, the

average power consumption drops to 80 mW × 4.2% or approxi-

mately 3.36 mW.

AD7899 DYNAMIC SPECIFICATIONS

The AD7899 is specified and 100% tested for dynamic perfor-

mance specifications as well as traditional dc specifications such

as Integral and Differential Nonlinearity. These ac specifications

are required for the signal processing applications such as phased

array sonar, adaptive filters, and spectrum analysis. These appli-

cations require information on the ADC’s effect on the spectral

content of the input signal. Hence, the parameters for which the

AD7899 is specified include SNR, harmonic distortion, inter-

modulation distortion, and peak harmonics. These terms are

discussed in more detail in the following sections.

Signal-to-Noise Ratio (SNR)

SNR is the measured signal-to-noise ratio at the output of the

ADC. The signal is the rms magnitude of the fundamental.

Noise is the rms sum of all the nonfundamental signals up to

half the sampling frequency (f

/2) excluding dc. SNR is dependent

upon the number of quantization levels used in the digitization

process; the more levels, the smaller the quantization noise. The

theoretical signal to noise ratio for a sine wave input is given by

SNR = (6.02N + 1.76) dB (1)

where N is the number of bits.

Thus for an ideal 14-bit converter, SNR = 86.04 dB.

Figure 9 shows a histogram plot for 8192 conversions of a dc

input using the AD7899 with 5 V supply. The analog input was

set at the center of a code transition. It can be seen that most of

the codes appear in one output bin, indicating very good noise

performance from the ADC.

1000

2000

3000

4000

5000

6000

7000

Figure 9. Histogram of 8192 Conversions of a DC Input

The output spectrum from the ADC is evaluated by applying a

sine wave signal of very low distortion to the analog input. A

Fast Fourier Transform (FFT) plot is generated from which the

SNR data can be obtained. Figure 10 shows a typical 4096 point

FFT plot of the AD7899 with an input signal of 100 kHz and a

sampling frequency of 400 kHz. The SNR obtained from this

graph is 80.5 dB. It should be noted that the harmonics are

taken into account when calculating the SNR.

2 3 4 5 6 7 8 9 10 11 12 13 14

CONVST/

CLKIN

EOC

CONVERSION

COMPLETE

START OF NEW

CONVERSION

(INPUT SAMPLED)

15 16

Figure 8. Continuous Conversion Mode

REV. A

AD7899

–13–

FREQUENCY – Hz

–140

0 50000

100000 150000 200000

= 400kHz

= 100kHz

SNR = 80.5dB

–120

–100

–80

–60

–40

–20

Figure 10. FFT Plot

Effective Number of Bits

The formula given in Equation 1 relates the SNR to the number

of bits. Rewriting the formula, as in Equation 2, it is possible to

obtain a measure of performance expressed in effective number

of bits (N).

N =

SNR −1. 7 6

6.02

(2)

The effective number of bits for a device can be calculated directly

from its measured SNR. Figure 11 shows a typical plot of effec-

tive number of bits versus frequency for an AD7899.

INPUT FREQUENCY – kHz

ENOB

100

1000 10000

–55ⴗC

+25ⴗC

+125ⴗC

Figure 11. Effective Numbers of Bits vs. Frequency

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and

fb, any active device with nonlinearities will create distortion

products at sum and difference frequencies of mfa ± nfb where

m, n = 0, 1, 2, 3 . . ., etc. Intermodulation terms are those for

which neither m nor n are equal to zero. For example, the sec-

ond order terms include (fa + fb) and (fa – fb) while the third

order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).

The AD7899 is tested using two input frequencies. In this case

the second and third order terms are of different significance.

The second order terms are usually distanced in frequency from

the original sine waves while the third order terms are usually at

a frequency close to the input frequencies. As a result, the

second and third order terms are specified separately. The cal-

culation of the intermodulation distortion is as per the THD

specification where it is the ratio of the rms sum of the indi-

vidual distortion products to the rms amplitude of the fundamental

expressed in dBs. In this case, the input consists of two, equal

amplitude, low distortion sine waves. Figure 12 shows a typical

IMD plot for the AD7899.

FREQUENCY – Hz

–140

0 50000

100000 150000 200000

–120

–100

–80

–60

–40

–20

Figure 12. IMD Plot

AC Linearity Plots

The plots in Figure 13 show typical DNL and INL for the

AD7899.

0 2000

4000 16000

1.00

ADC – Code

–1.00

INL – LSB

6000 8000 10000 12000 14000

–0.50

0.50

0 2000

4000 16000

1.00

ADC – Code

–1.00

DNL – LSB

6000 8000 10000 12000 14000

–0.50

0.50

Figure 13. Typical DNL and INL Plots

REV. A

AD7899

–14–

MICROPROCESSOR INTERFACING

The high-speed parallel interface of the AD7899 allows easy

interfacing to most DSPs and microprocessors. The AD7899

interface of the AD7899 consists of the data lines (DB0 to DB13),

CS, RD, and BUSY/EOC.

AD7899–ADSP-21xx Interface

Figure 14 shows an interface between the AD7899 and the

ADSP-21xx. The CONVST signal can be generated by the

ADSP-21xx or from some other external source. Figure 14 shows

the CS being generated by a combination of the DMS signal and

the address bus of the ADSP-21xx. In this way the AD7899 is

mapped into the data memory space of the ADSP-21xx.

The AD7899 BUSY/EOC line provides an interrupt to the

ADSP-21xx when the conversion is complete. The conversion

result can then be read from the AD7899 using a read operation.

The AD7899 is read using the following instruction

MR0 = DM(ADC)

where MR0 is the ADSP-21xx MR0 register and ADC is the

AD7899 address.

CONVST

DB0–DB13

AD7899

DT1/F0

IRQn

D8–D21

A0–A13

ADSP-21xx

ADDRESS

DECODE

DMS

BUSY/EOC

Figure 14. AD7899–ADSP-21xx Interface

AD7899–TMS320C5x Interface

Figure 15 shows an interface between the AD7899 and the

TMS320C5x. As with the previous interfaces, conversion can be

initiated from the TMS320C5x or from an external source and

the processor is interrupted when the conversion sequence is

completed. The CS signal to the AD7899 derived from the DS

signal and a decode of the address bus. This maps the AD7899

into external data memory. The RD signal from the TMS320 is

used to enable the ADC data onto the data bus. The AD7899 has

a fast parallel bus so there are no wait state requirements. The

following instruction is used to read the conversion results from

the AD7899:

IN D,ADC

where D is Data Memory address and ADC is the AD7899

address.

BUSY/EOC

CONVST

DB0–DB13

AD7899

PA0

INTn

D0–D13

A0–A13

TMS320C5x

ADDRESS

DECODE

Figure 15. AD7899–TMS320C5x Interface

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P17

AD7899BRZ-1

Mfr. #:

Buy AD7899BRZ-1

Manufacturer:

Analog Devices Inc.

Description:

Analog to Digital Converters - ADC 5V SGL Supply 14-Bit 400 kSPS

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AD7899BRZ-1

AD7899BRZ-1

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