REV. A
AD7899
–6–
PIN FUNCTION DESCRIPTIONS
Pin
No. Mnemonic Description
1V
REF
Reference Input/Output. This pin is provides access to the internal reference (2.5 V ± 20 mV) and
also allows the internal reference to be overdriven by an external reference source (2.5 V ± 5%).
A 0.1 µF decoupling capacitor should be connected between this pin and GND.
2, 6 GND Ground Pin. This pin should be connected to the systems analog ground
plane.
3, 4 V
INB
, V
INA
Analog Inputs. See Analog Input Section.
5V
DD
Positive Supply Voltage, 5.0 V ± 5%.
713 DB13DB7 Data Bit 13 is the MSB, followed by Data Bit 12 to Data Bit 7. Three-state outputs.
14 OPGND Output Driver Ground. This is the ground pin of the output drivers for D13 to D0 and BUSY/EOC. It should
be connected to the systems analog ground plane
.
15 V
DRIVE
This pin provides the positive supply voltage for the digital inputs and outputs. It is normally tied to V
DD
but may also be powered by a 3 V ± 10% supply which allows the inputs and outputs to be interfaced
to 3 V processors and DSPs. V
DRIVE
should be decoupled with a 0.1 µF capacitor to GND.
1622 DB6DB0 Data Bit 6 to Data Bit 0. Three-state Outputs.
23 BUSY/EOC BUSY/EOC Output. Digital output pin used to signify that a conversion is in progress or that a conversion
has finished. The function of the BUSY/EOC is determined by the state of CONVST at the end of con-
version. See the Timing and Control Section.
24 RD Read Input. Active low logic input which is used in conjunction with CS low to enable the data outputs.
25 CS Chip Select Input. Active low logic input. The device is selected when this input is active.
26 CONVST Convert Start Input. Logic Input. A low to high transition on this input puts the track/hold into hold mode
and starts conversion.
27 CLKIN Conversion Clock Input. CLKIN is an externally applied clock which allows the user to control the
conversion rate of the AD7899. If the CLKIN input is high on the rising edge of CONVST an externally
applied clock will be used as the conversion clock. If the CLKIN is low on the rising edge of CONVST
the internal laser-trimmed oscillator is used as the conversion clock. Each conversion needs sixteen clock
cycles in order for the conversion to be completed. The externally applied clock should have a duty cycle
no greater than 60/40. The CLKIN pin can be tied to GND if an external clock is not required.
28 STBY Standby Mode Input. Logic input which is used to put the device into the power save or standby mode.
The STBY input is high for normal operation and low for standby operation.
PIN CONFIGURATION
SOIC/SSOP
TOP VIEW
(Not to Scale)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AD7899
OPGND
DB7
DB8
DB9
DB10
DB11
DB12
V
REF
GND
V
INB
V
INA
DB13
GND
V
DD
V
DRIVE
DB6
DB5
DB4
DB3
DB2
DB1
STBY
CLKIN
CONVST
CS
DB0
BUSY/EOC
RD
REV. A
AD7899
–7–
TERMINOLOGY
Signal to (Noise + Distortion) Ratio
This is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (f
S
/2), excluding dc.
The ratio is dependent upon the number of quantization levels
in the digitization process; the more levels, the smaller the quan-
tization noise. The theoretical signal to (noise + distortion) ratio
for an ideal N-bit converter with a sine wave input is given by:
Signal to (Noise + Distortion) = (6.02N + 1.76) dB
Thus for a 14-bit converter, this is 86.04 dB.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7899 it is defined
as:
THD dB
VVVVV
V
( ) log=
++++
20
2
2
3
2
4
2
5
2
6
2
1
where V
1
is the rms amplitude of the fundamental and V
2
, V
3
,
V
4
, and V
5
are the rms amplitudes of the second through the
fifth harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to f
S
/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is deter-
mined by the largest harmonic in the spectrum, but for parts
where the harmonics are buried in the noise floor, it will be a
noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which
neither m nor n are equal to zero. For example, the second order
terms include (fa + fb) and (fa fb), while the third order terms
include (2fa + fb), (2fa fb), (fa + 2fb) and (fa 2fb).
The AD7899 is tested using two input frequencies. In this case, the
second and third order terms are of different significance. The
second order terms are usually distanced in frequency from the
original sine waves while the third order terms are usually at a
frequency close to the input frequencies. As a result, the second
and third order terms are specified separately. The calculation
of the intermodulation distortion is as per the THD speci-
fication where it is the ratio of the rms sum of the individual
distortion products to the rms amplitude of the fundamental
expressed in dBs.
Differential Nonlinearity
This is the difference between the measured and the ideal
1 LSB change between any two adjacent codes in the ADC.
Positive Gain Error (AD7899-1, AD7899-3)
This is the deviation of the last code transition (01 . . . 110 to
01 . . . 111) from the ideal 4 × V
REF
3/2 LSB (AD7899 at
± 10 V), 2 × V
REF
3/2 LSB (AD7899 at ± 5 V range) or V
REF
3/2 LSB (AD7899 at ± 2.5 V range) after the Bipolar Offset
Error has been adjusted out.
Positive Gain Error (AD7899-2)
This is the deviation of the last code transition (11 . . . 110 to
11 . . . 111) from the ideal 2 × V
REF
3/2 LSB (AD7899 at
± 10 V), 2 × V
REF
3/2 LSB (AD7899 at 0 V to 5 V range) or
V
REF
3/2 LSB (AD7899 at 0 V to 2.5 V range) after the Uni-
polar Offset Error has been adjusted out.
Unipolar Offset Error (AD7899-2)
This is the deviation of the first code transition (00 . . . 00 to
00 . . . 01) from the ideal AGND +1/2 LSB
Bipolar Zero Error (AD7899-1, AD7899-2)
This is the deviation of the midscale transition (all 0s to all 1s)
from the ideal AGND 1/2 LSB.
Negative Gain Error (AD7899-1, AD7899-3)
This is the deviation of the first code transition (10 . . . 000 to
10 . . . 001) from the ideal 4 × V
REF
+ 1/2 LSB (AD7899 at
± 10 V), 2 × V
REF
+ 1/2 LSB (AD7899 at ±5 V range) or V
REF
+ 1/2 LSB (AD7899 at ±2.5 V range) after Bipolar Zero Error
has been adjusted out.
Track/Hold Acquisition Time
Track/Hold acquisition time is the time required for the output
of the track/hold amplifier to reach its final value, within ± 1/2 LSB,
after the end of conversion (the point at which the track/hold
returns to track mode). It also applies to situations where there
is a step input change on the input voltage applied to the selected
V
INA/VINB
input of the AD7899. It means that the user must wait
for the duration of the track/hold acquisition time after the end
of conversion or after a step input change to V
INA
/V
INB
before
starting another conversion, to ensure that the part operates to
specification.
REV. A
AD7899
–8–
CONVERTER DETAILS
The AD7899 is a high-speed, low-power, 14-bit A/D converter
that operates from a single 5 V supply. The part contains a
2.2 µs successive-approximation ADC, track/hold amplifier, an
internal 2.5 V reference and a high-speed parallel interface. The
part accepts an analog input range of ±10 V or ± 5 V (AD7899-1),
0 V to 2.5 V or 0 V to 5 V (AD7899-2) and ± 2.5 V (AD7899-3).
Overvoltage protection on the analog inputs for the part allows
the input voltage to go to ±18 V (AD7899-1 with ± 10 V input
range), 9 V to +18 V (AD7899-1 with ± 5 V input range), 1 V
to +18 V (AD7899-2) and 4 V to +18 V (AD7899-3) without
causing damage.
A conversion is initiated on the AD7899 by pulsing the CONVST
input. On the rising edge of CONVST, the on-chip track/hold is
placed into hold and the conversion is started. The BUSY/EOC
output signal is triggered high on the rising edge of CONVST
and will remain high for the duration of the conversion sequence.
The conversion clock for the part is generated internally using a
laser-trimmed clock oscillator circuit. There is also the option of
using an external clock. An external noncontinuous clock is applied
to the CLKIN pin. If, on the rising edge of CONVST, this input
is high, the external clock will be used. The external clock should
not start until 100 ns after the rising edge of CONVST. The
optimum throughput is obtained by using the internally gener-
ated clocksee Using an External Clock. The BUSY/EOC signal
indicates the end of the conversion, and at this time the Track and
Hold returns to tracking mode. The conversion results can be
read at the end of the conversion (indicated by BUSY/EOC
going low) via a 14-bit parallel data bus with standard CS and RD
signalssee Timing and Control.
Conversion time for the AD7899 is 2.2 µs and the track/hold
acquisition time is 0.3 µs. To obtain optimum performance from
the part, the read operation should not occur during a conversion
or during the 150 ns prior to the next CONVST rising edge.
This allows the part to operate at throughput rates up to 400 kHz
and achieve data sheet specifications.
CIRCUIT DESCRIPTION
Track/Hold Section
The track/hold amplifier on the AD7899 allows the ADCs to
accurately convert an input sine wave of full-scale amplitude to
14-bit accuracy. The input bandwidth of the track/hold is greater
than the Nyquist rate of the ADC even when the ADC is oper-
ated at its maximum throughput rate of 400 kSPS (i.e., the
track/hold can handle input frequencies in excess of 200 kHz).
The track/hold amplifiers acquire input signals to 14-bit
accuracy in less than 300 ns The operation of the track/hold is
essentially transparent to the user. The track/hold amplifier
samples the input channel on the rising edge of CONVST. The
aperture time for the track/hold (i.e., the delay time between the
external CONVST signal and the track/hold actually going into
hold) is typically 15 ns and, more importantly, is well matched
from device to device. It allows multiple AD7899s to sample
more than one channel simultaneously. At the end of a conversion,
the part returns to its tracking mode. The acquisition time of
the track/hold amplifier begins at this point.
Reference Section
The AD7899 contains a single reference pin, labelled
V
REF
,
which either provides access to the parts own 2.5 V reference or
allows an external 2.5 V reference to be connected to provide
the reference source for the part. The part is specified with a
2.5 V reference voltage.
To use the internal reference as the reference source for the
AD7899, simply connect a 0.1 µF capacitor from the
V
REF
pin
to AGND. The voltage that appears at this pin is internally
buffered before being applied to the ADC. If this reference is
required for use external to the AD7899, it should be buffered,
as the part has a FET switch in series with the reference output
resulting in a source impedance for this output of 6 knominal.
The tolerance on the internal reference is ± 10 mV at 25°C with
a typical temperature coefficient of 25 ppm/°C and a maximum
error over temperature of ± 20 mV.
If the application requires a reference with a tighter tolerance or
the AD7899 needs to be used with a system reference, the user
has the option of connecting an external reference to this
V
REF
pin. The external reference will effectively overdrive the internal
reference and thus provide the reference source for the ADC.
The reference input is buffered before being applied to the ADC
with the maximum input current of ± 100 µA. Suitable reference
sources for the AD7899 include the AD680, AD780, REF192,
and REF43 precision 2.5 V references.
Analog Input Section
The AD7899 is offered as three part types, the AD7899-1 where
the input can be configured for ± 10 V or a ± 5 V input voltage
range, the AD7899-2 where the input can be configured for 0 V
to 5 V or a 0 V to 2.5 V input voltage range and the AD7899-3
which handles input voltage range ± 2.5 V. The amount of current
flowing into the analog input will depend on the analog input
range and the analog input voltage. The maximum current flows
when negative full-scale is applied.
AD7899-1
Figure 2 shows the analog input section of the AD7899-1. The
input can be configured for ± 5 V or ± 10 V operation on the
AD7899-1. For ±5 V operation, the V
INA
and V
INB
inputs are
tied together and the input voltage is applied to both. For ± 10 V
operation, the V
INB
input is tied to AGND and the input voltage
is applied to the V
INA
input. The V
INA
and V
INB
inputs are sym-
metrical and fully interchangeable.

AD7899BRZ-1

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 5V SGL Supply 14-Bit 400 kSPS
Lifecycle:
New from this manufacturer.
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