MARCH 9, 2017 7 9-OUTPUT 1.5V PCIE GEN1-2-3 FANOUT BUFFER WITH ZO=100OHMS
9DBU0941 DATASHEET
Electrical Characteristics–DIF Low-Power HCSL Outputs
Electrical Characteristics–Current Consumption
TA = T
AMB,
Supply voltages per normal operation conditions; see Test Loads for loading conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
dV/dt Scope averaging on, fast setting 1 2.4 3.5
V/ns
1,2,3
dV/dt Scope averaging on, slow setting 0.7 1.7 2.5
V/ns
1,2,3
Slew Rate Matching
Δ
dV/dt Slew rate matching, scope averaging on 9 20
%
1,2,4
Voltage High V
HIGH
630 750 850 7
Voltage Low V
LOW
-150 26 150 7
Max Voltage Vmax 763 1150 7
Min Voltage Vmin -300 22 7
Vswing Vswing Scope averaging off 300 1448 mV 1,2
Crossing Voltage (abs) Vcross_abs Scope averaging off 250 390 550 mV 1,5
Crossing Voltage (var)
Δ
-Vcross Scope averaging off 11 140 mV 1,6
2
Measured from differential waveform
7
At default SMBus settings.
Slew Rate
Statistical measurement on single-ended signal
using oscilloscope math function. (Scope
averaging on)
mV
Measurement on single ended signal using
absolute value. (Scope averaging off)
mV
1
Guaranteed by design and characterization, not 100% tested in production.
3
Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4
Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on
the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5
Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
6
The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross
absolute) allowed. The intent is to limit Vcross induced modulation by setting
Δ
-Vcross to be smaller than Vcross absolute.
TA = T
AMB
; Supply voltages per normal operation conditions; see Test Loads for loading conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
I
DDA
VDDO1.5+VDDR, at 100MHz
2.3
3mA
I
DDx
VDDx, All outputs active at 100MHz
4.5
6mA
I
DDIO
VDDIO, All outputs active at 100MHz
33
40 mA
I
DDAPD
VDDO1.5+VDDR, CKPWRGD_PD# = 0 0.4 1 mA
2
I
DDxPD
VDDx, CKPWRGD_PD# = 0 0.2 0.6 mA
2
I
DDIOPD
VDDIO, CKPWRGD_PD# = 0 0.001 0.1 mA
2
1
Guaranteed by design and characterization, not 100% tested in production.
2
Input clock stopped.
Operating Supply Current
Powerdown Current
9-OUTPUT 1.5V PCIE GEN1-2-3 FANOUT BUFFER WITH ZO=100OHMS 8 MARCH 9, 2017
9DBU0941 DATASHEET
Electrical Characteristics–Output Duty Cycle, Jitter, Skew and PLL Characteristics
Electrical Characteristics–Phase Jitter Parameters
TA = T
AMB,
Supply voltages per normal operation conditions; see Test Loads for loading conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Duty Cycle Distortion t
DCD
Measured differentially, at 100MHz -1 -0.2 0.5 % 1,3
Skew, Input to Output t
p
dBYP
V
T
= 50% 2400 2862 3700 ps 1
Skew, Output to Output t
sk3
V
T
= 50% 30 60 ps 1,4
Jitter, Cycle to Cycle t
jcyc-cyc
Additive Jitter 0.1 5 ps 1,2
1
Guaranteed by design and characterization, not 100% tested in production.
2
Measured from differential waveform.
3
Duty cycle distortion is the difference in duty cycle between the output and the input clock.
4
All outputs at default slew rate.
TA = T
AMB,
Supply voltages per normal operation conditions; see Test Loads for loading conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX
INDUSTRY
LIMIT UNITS Notes
t
jp
hPCIeG1
PCIe Gen 1 0.1 5 N/A ps (p-p) 1,2,3,5
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
0.1 0.4 N/A
ps
(rms)
1,2,3,4,
5
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
0.1 0.7 N/A
ps
(rms)
1,2,3,4
t
jphPCIeG3
PCIe Gen 3
(2-4MHz or 2-5MHz, CDR = 10MHz)
0.1 0.3 N/A
ps
(rms)
1,2,3,4
t
jphSGMIIM0
125MHz, 1.5MHz to 10MHz, -20dB/decade
rollover < 1.5MHz, -40db/decade rolloff > 10MHz
200 250 N/A
fs
(rms)
1,6
t
jphSGMIIM1
125MHz, 12kHz to 20MHz, -20dB/decade rollover
< 1.5MHz, -40db/decade rolloff > 10MHz
313 350 N/A
fs
(rms)
1,6
1
Guaranteed by design and characterization, not 100% tested in production.
4
For RMS figures, additive jitter is calculated by solving the following equation: Additive jitter = SQRT[(total jitter)^2 - (input jitter)^2].
5
Driven by 9FGV0831 or equivalent.
6
Rohde & Schwarz SMA100.
3
Sample size of at least 100K cycles. This figure extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
Additive Phase Jitter
t
jphPCIeG2
2
See http://www.pcisig.com for complete specs.
MARCH 9, 2017 9 9-OUTPUT 1.5V PCIE GEN1-2-3 FANOUT BUFFER WITH ZO=100OHMS
9DBU0941 DATASHEET
Additive Phase Jitter Plot: 125M (12kHz to 20MHz)
RMS additive jitter: 313fs

9DBU0941AKILF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Buffer 2 O/P 1.5V PCIE 56mW GEN1-2-3 Ind 100ohm
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet