7
LT1160/LT1162
11602fb
+
V
SV
+
PV
+
IN TOP
IN BOTTOM
UV OUT
SGND
PGND
BOOST
T GATE DR
T GATE FB
T SOURCE
B GATE DR
B GATE FB
3k
50
50
1µF
1µF
3000pF
3000pF
1160/62 TC01
(LT1160)
+
V/I
+
V/I
+
V
+
V
TEST CIRCUIT
+
+
SV
+
IN TOP
IN BOTTOM
BOOST
T GATE DR
T GATE FB
T SOURCE
PV
+
B GATE DR
B GATE FB
1160/62 BD
SGND
PGND
GND
1/2 LT1162
LT1160
BIAS
3k
3k
TOP
UV LOCK
BOTTOM
UV LOCK
2.9V
2.5V
5V
5V
UV OUT
FUNCTIONAL DIAGRA
UU
W
(LT1160 or 1/2 LT1162)
(LT1160 or 1/2 LT1162)
8
LT1160/LT1162
11602fb
TI I G DIAGRA
UWW
OPERATIO
U
(Refer to Functional Diagram)
The LT1160 (or 1/2 LT1162) incorporates two indepen-
dent driver channels with separate inputs and outputs. The
inputs are TTL/CMOS compatible; they can withstand
input voltages as high as V
+
. The 1.4V input threshold is
regulated and has 300mV of hysteresis. Both channels are
noninverting drivers. The internal logic prevents both
outputs from simultaneously turning on under any input
conditions. When both inputs are high both outputs are
actively held low.
The floating supply for the top driver is provided by a
bootstrap capacitor between the Boost pin and the Top
Source pin. This capacitor is recharged each time the
negative plate goes low in PWM operation.
The undervoltage detection circuit disables both channels
when V
+
is below the undervoltage trip point. A separate
UV detect block disables the high side channel when
V
BOOST
– V
TSOURCE
is below its own undervoltage trip
point.
The top and bottom gate drivers in the LT1160 each utilize
two gate connections: 1) a gate drive pin, which provides
the turn on and turn off currents through an optional series
gate resistor, and 2) a gate feedback pin which connects
directly to the gate to monitor the gate-to-source voltage.
Whenever there is an input transition to command the
outputs to change states, the LT1160 follows a logical
sequence to turn off one MOSFET and turn on the other.
First, turn-off is initiated, then V
GS
is monitored until it has
decreased below the turn-off threshold, and finally the
other gate is turned on.
10V
2V
IN TOP
IN BOTTOM
TOP GATE
DRIVER
BOTTOM
GATE
DRIVER
2V
0.8V
2V
0.8V
12V
0V
12V
0V
t
r
t
D1
t
D3
10V
2V
t
r
t
D2
t
D4
t
f
t
D3
t
D2
t
f
t
D4
1160/62 TD
t
D1
9
LT1160/LT1162
11602fb
Power MOSFET Selection
Since the LT1160 (or 1/2 LT1162) inherently protects the
top and bottom MOSFETs from simultaneous conduction,
there are no size or matching constraints. Therefore selec-
tion can be made based on the operating voltage and
R
DS(ON)
requirements. The MOSFET BV
DSS
should be
greater than the HV and should be increased to approxi-
mately (2)(HV) in harsh environments with frequent fault
conditions. For the LT1160 maximum operating HV supply
of 60V, the MOSFET BV
DSS
should be from 60V to 100V.
The MOSFET R
DS(ON)
is specified at T
J
= 25°C and is
generally chosen based on the operating efficiency re-
quired as long as the maximum MOSFET junction tem-
perature is not exceeded. The dissipation while each
MOSFET is on is given by:
P = D(I
DS
)
2
(1+)R
DS(ON)
Where D is the duty cycle and is the increase in R
DS(ON)
at the anticipated MOSFET junction temperature. From this
equation the required R
DS(ON)
can be derived:
R
P
DI
DS ON
DS
()
=
()
+
()
2
1
For example, if the MOSFET loss is to be limited to 2W
when operating at 5A and a 90% duty cycle, the required
R
DS(ON)
would be 0.089/(1 + ). (1 + ) is given for each
MOSFET in the form of a normalized R
DS(ON)
vs tempera-
ture curve, but = 0.007/°C can be used as an approxima-
tion for low voltage MOSFETs. Thus, if T
A
= 85°C and the
available heat sinking has a thermal resistance of 20°C/W,
the MOSFET junction temperature will be 125°C and
= 0.007(125 – 25) = 0.7. This means that the required
R
DS(ON)
of the MOSFET will be 0.089/1.7 = 0.0523,
which can be satisfied by an IRFZ34 manufactured by
International Rectifier.
Transition losses result from the power dissipated in each
MOSFET during the time it is transitioning from off to on,
or from on to off. These losses are proportional to (f)(HV)
2
and vary from insignificant to being a limiting factor on
operating frequency in some high voltage applications.
APPLICATIONS INFORMATION
WUU
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Paralleling MOSFETs
When the above calculations result in a lower R
DS(ON)
than
is economically feasible with a single MOSFET, two or
more MOSFETs can be paralleled. The MOSFETs will
inherently share the currents according to their R
DS(ON)
ratio as long as they are thermally connected (e.g., on a
common heat sink). The LT1160 top and bottom drivers
can each drive five power MOSFETs in parallel with only a
small loss in switching speeds (see Typical Performance
Characteristics). A low value resistor (10 to 47) in
series with each individual MOSFET gate may be required
to “decouple” each MOSFET from its neighbors to prevent
high frequency oscillations (consult manufacturer’s rec-
ommendations). If gate decoupling resistors are used the
corresponding gate feedback pin can be connected to any
one of the gates as shown in Figure 1.
Driving multiple MOSFETs in parallel may restrict the
operating frequency to prevent overdissipation in the
LT1160 (see the following Gate Charge and Driver Dissi-
pation).
Gate Charge and Driver Dissipation
A useful indicator of the load presented to the driver by a
power MOSFET is the total gate charge Q
G
, which includes
the additional charge required by the gate-to-drain swing.
Q
G
is usually specified for V
GS
= 10V and V
DS
= 0.8V
DS(MAX)
.
When the supply current is measured in a switching
application, it will be larger than given by the DC electrical
characteristics because of the additional supply current
associated with sourcing the MOSFET gate charge:
II
dQ
dt
dQ
dt
SUPPLY DC
G
TOP
G
BOTTOM
=+
+
GATE DR
GATE FB
LT1160
R
G
*
R
G
*
*OPTIONAL 10
1160 F01
Figure 1. Paralleling MOSFETs

LT1160CS#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Gate Drivers Half-/Full-Bridge N-Ch Pwr MOSFET Drvrs
Lifecycle:
New from this manufacturer.
Delivery:
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