SAA1305T/N1,112 Datasheet SAA1305T/N1,112, SAA1305T/N1,118 | P13-P15

2004 Jan 15 13

Philips Semiconductors Product speciﬁcation

On/off logic IC SAA1305T

Write mode operations

After a START condition the master sends a device select

code with the R/W bit reset to logic 0; see Fig.8. The IC

acknowledge this and waits for the address byte. After the

address the master sends the corresponding data, which

is acknowledged by the IC. It is possible to continue with

the data transfer, each byte is acknowledged by the IC.

The internal byte address counter is incremented after

each data transmission.

The transfer is terminated when the master generates a

STOP condition. In the event of a wrong address decoding

the IC sends a no acknowledge signal and ignores all

following data.

Figure 9 shows the sequence for write data mode. Both

alarm and watch registers consist of 3 bytes. The first byte

(2 and 5) is the most significant byte. The definitions of the

bits are given in Tables 8, 10, 14 and 15.

Fig.8 I

C-bus write mode sequence.

handbook, full pagewidth

S PDEVICE SELECT ADDRESS

acknowledge

DATA 1 DATA N

R/W

START

condition

STOP

condition

acknowledge acknowledge acknowledge acknowledge

MGR223

Fig.9 I

C-bus write data sequence.

handbook, full pagewidth

MGR224

START DEVICE SELECT ADDRESS CONTROL LED ALARM WATCH IMPEDANCE

byte 0 1 2, 3, 4 5, 6, 7 8

STOP

2004 Jan 15 14

Philips Semiconductors Product speciﬁcation

On/off logic IC SAA1305T

Table 8 Deﬁnition of the control register bits

BIT DESCRIPTION

7 part of the mask register; corresponds to input D7; a logic 1 disables input D7 (no inﬂuence on pin CHI)

6 part of the mask register; corresponds to input D6; a logic 1 disables input D6 (no inﬂuence on pin CHI)

5 part of the mask register; corresponds to input D5; a logic 1 disables input D5 (no inﬂuence on pin CHI)

4 part of the mask register; corresponds to input D4; a logic 1 disables input D4 (no inﬂuence on pin CHI)

3 content of bits 3 and 2 corresponds with the pulse width of the reset pulse output; see Table 9

1 control bit for pin ON/OFF; a logic 0 sets pin ON/OFF to V

; a logic 1 sets pin ON/OFF to V

0 control bit (ENABLE-RESET) for the IC modes; only setting a logic 0 is possible; standby mode with disabled

Watchdog timer, enabled reset generation, ON/OFF = LOW and CHI = 3-state; with the rising edge of the

reset pulse output the IC enters the run mode with enabled Watchdog timer, disabled reset generation,

ON/OFF = HIGH (but controllable via control register bit 1) and CHI = HIGH (is active, not in 3-state)

Table 9 Pulse width of the reset pulse output

Table 10 Deﬁnition of the LED register bits

Table 11 Function control bits

BIT 3 BIT 2 PULSE WIDTH (ms)

00 20

01 10

10 5

11 1

BIT DESCRIPTION

7 bits 7 and 6 are function control bits;

see Table 11

5 no function

4 reset I

C-bus error counter

3 bits 3 and 2 are control bits for the blink LED

frequency (output LOW time); see Table 12

1 bits 1 and 0 are control bits for the blink LED

duration time; see Table 13

BIT 7 BIT 6 FUNCTION

0 0 LED output switched to ground

0 1 blink function according the LED

1 0 LED output switched to V

1 1 blink function according the LED

Table 12 Control bits for the blink LED frequency

Table 13 Control bits for the blink LED duration time

BIT 3 BIT 2 FREQUENCY

0 0 2 Hz (0.5 s)

0 1 1 Hz (1 s)

1 0 0.67 Hz (1.5 s)

1 1 0.5 Hz (2 s)

BIT 1 BIT 0 DURATION TIME (ms)

00 20

01 30

10 40

11 50

2004 Jan 15 15

Philips Semiconductors Product speciﬁcation

On/off logic IC SAA1305T

Table 14 Deﬁnition of the watch and alarm register bits (write mode); notes 1, 2 and 3

Notes

1. The alarm is disabled by writing a time larger than 24:00:00. With the default values the alarm function is disabled.

The alarm is also disabled if hours >23 or minutes >59 or seconds >59.

2. There are several attention points if a senseless time is written to the alarm register, for example:

a) Write 25 to address 2; data bits 4 to 0 = 25 ⇒ hours = 25 (alarm disabled).

b) Write 70 to address 3; data bits 5 to 0 = 6 ⇒ minutes = 6.

c) Write 81 to address 4; data bits 5 to 0 = 17 ⇒ seconds = 17.

3. There are several attention points if a senseless time is written to the watch register, for example:

a) Write 25 to address 5; data bits 4 to 0 = 25 ⇒ hours = 23 (limited).

b) Write 70 to address 6; data bits 5 to 0 = 6 ⇒ minutes = 6.

c) Write 81 to address 7; data bits 5 to 0 = 17 ⇒ seconds = 17.

Table 15 Deﬁnition of the impedance register bits

Table 16 Control bits for the impedance detection delay time

ADDRESS (HEX) DATA BITS DESCRIPTION VALUES DEFAULT

2 4 to 0 hours of alarm 0 to 31 31

3 5 to 0 minutes of alarm 0 to 63 63

4 5 to 0 seconds of alarm 0 to 63 63

5 4 to 0 hours of watch 0 to 23 0

6 5 to 0 minutes of watch 0 to 59 0

7 5 to 0 seconds of watch 0 to 59 0

BIT DESCRIPTION

7 no function

6 no function

5 no function

4 no function

3 no function

2 enable or disable bit for the impedance detection

0 = inactive (

⁄

detection without influence on the status register)

1 = active (

⁄

detection with influence on the status register)

1 bits 1 and 0 are control bits for the impedance detection delay time; see Table 16

BIT 1 BIT 0 DELAY TIME

0 0 100 ms

0 1 250 ms

1 0 500 ms

11 1s

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SAA1305T/N1,112

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Encoders, Decoders, Multiplexers & Demultiplexers ANALOG AUDIO MISC

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