SAA1305T/N1,112 Datasheet SAA1305T/N1,112, SAA1305T/N1,118 | P7-P9

2004 Jan 15 7

Philips Semiconductors Product speciﬁcation

On/off logic IC SAA1305T

Serial I/O

The hardware of the I

C-bus interface (slave) operates

with a maximum clock frequency of 400 kHz.

Inputs

Pins D0 to D7 are connected to latches (new register).

Each latch contains and stores the input change until the

read out via the I

C-bus (read out of new register).

A second register (old register, latches) contains the input

situation before a ‘reset pulse’ signal or HIGH-to-LOW

transition of pin CHI. After a level change on any of the

inputs D0 to D7 (content of new register into ‘old’ register),

pin CHI will indicate this event. Reading the ‘old’ register

has no influence on any latch content. Reading the new

the I

C-bus read sequence of the new register the latch

content will be shifted into the corresponding old latch and

afterwards the new latches are enabled until the next

change on this input. The functions of the inputs D0 to D7

are shown in Table 1.

Due to the fact, that a ‘reset pulse’ signal or a ‘change

information’ signal are also possible via the Watchdog

timer, V

timer, alarm timer, impedance detection,

oscillator fault or after a device reset, the information about

these different events is also available via corresponding

bits within the status register; see Table 5.

A status I

C-bus read sequence resets the status register

and pin CHI. Only after a change on any of the inputs

D0 to D7, an I

C-bus read sequence of the status register,

old register and new register is it necessary to reset

pin CHI. The inputs D4 to D7 are maskable via the

C-bus; see Table 8. All masked inputs (defined via the

control register) are blocked to trigger pins CHI and RP.

During the disable phase of the masked inputs the

corresponding bits within the old and new registers will be

continuously refreshed with the actual input level.

Table 1 Input logic levels and functions

INPUT

SCHMITT

TRIGGER INPUT

SPECIAL INPUT MASKABLE

TIMER

INTERRUPT

IMPEDANCE

DETECTION

D7 X − X −−

D6 X − X −−

D5 X − X −−

D4 − XX−−

D3 − X −−−

D2 − X −−−

D1 X −−−X

D0 X −−X −

2004 Jan 15 8

Philips Semiconductors Product speciﬁcation

On/off logic IC SAA1305T

IMPEDANCE DETECTION

Input D1 is a normal input with comparable behaviour like

the other seven inputs. The only difference is an additional

internal exclusive-NOR (EXNOR) connected between the

two comparator outputs for high and low detection;

see Fig.4. The EXNOR signal indicates, in combination

with a special external circuit on input D1, a voltage of

⁄

on this input.

The simple input description for impedance detection is

probably not the real solution, but helps to explain the

function. Input D1 can be used as a normal input and for

impedance detection as described in Table 2. For normal

use the output Q acts like every other input, but for

impedance detection the EXNOR output S is also

important. Output S is linked to the status register bit 6 and

indicates the

⁄

; see Table 5.

Between detection and indication via the status register

bit 6, a delay time is integrated (programmable via the

impedance register bits 1 and 0; see Table 15). When the

⁄

value is detected the EXNOR output will be set to

logic 1 (active) and after the programmed delay time the

status register bit 6 will be set to logic 1 (active). This event

will also be indicated via pin CHI and (if enabled) pin RP.

The impedance information (bit 6 is active) within the

status register is present until the I

C-bus status is read.

With the disappearance of the impedance information no

further actions will be generated. Every impedance signal

change during the delay time will restart the delay time.

However an impedance detection is only possible in the

event of a stable signal, at least for the programmed delay

time. Setting the status register bit 6 with a repetition time

which equals the ‘impedance delay time’ as long as

input D1 stays in high-impedance state is implemented.

Fig.4 Simple input description for impedance detection.

handbook, full pagewidth

MGR203

1.5 V

3.5 V

5 V12 V

10 kΩ

100 kΩ

input D1

ignition

key

Table 2 Logic levels for impedance detection

IGNITION KEY O1 O2 Q S

12V 1010

Open-circuit (V

= 2.5 V) 0 0 0 or 1 1

Ground (V

<1.5V) 0100

2004 Jan 15 9

Philips Semiconductors Product speciﬁcation

On/off logic IC SAA1305T

Watchdog timer

An internal Watchdog timer is active after each reset pulse

output and can be triggered via pin WD. In the event of a

not specified pulse, a delayed or missing trigger pulse, a

reset on pin RP will be the immediate reaction.

After the HIGH-to-LOW transition of the reset pulse output,

the first transition change within 500 ms on pin WD will be

detected as the first trigger from the microcontroller. The

timing diagram for the Watchdog timer trigger signal is

shown in Fig.5.

Fig.5 Watchdog timer trigger timing.

(1) In the event of a not specified, a delayed or missing trigger signal, a reset on pin RP will be the immediate reaction.

(2) The maximum time until signal change for first Watchdog timer is 500 ms.

(3) The time until next signal change is minimum 200 ms and maximum 300 ms.

handbook, halfpage

MGR220

(3)

(1)

(2)

Oscillators

Two oscillator types are built-in, a RC oscillator (designed

for 32.768 kHz) and a crystal oscillator (32.768 kHz), both

with separate pins. For a proper device function an

oscillator control circuit is integrated. This circuit

supervises the oscillator function and creates a reset and

oscillator restart in the event of an oscillator failure.

In the event of an oscillator fault, the event will be indicated

after a restart via the status register bit 5. During the

oscillator failure phase some outputs remain at a defined

level as shown in Table 3.

The RC oscillator accuracy is 5%.

When operating with the RC oscillator, pin XTAL2 must be

connected to V

or V

to minimize the quiescent

current. When operating with the crystal oscillator

pin OSC2 must be connected to V

or V

timer

A built-in timer, which can be started with a HIGH-to-LOW

transition on pin

TS, triggers, after 250 ms, pins RP

and CHI and sets pin ON/OFF. The V

timer starts only

once after a valid start condition. Default state after a

Power-on reset is not active. A V

timer start resets the

Watchdog timer. During run time of the V

timer is

ON/OFF = LOW, CHI = 3-state and the Watchdog timer is

disabled.

Pin TS is only active during the run mode. During run time

of the V

timer the IC remains in the wait mode. Only a

HIGH-level signal on input D0 can stop the V

timer in the

same way as after 250 ms. In the event of an oscillator

fault the IC also enters the run mode but without an

influence on the status register bit 2. During the wait mode

an influence of the status register via other sources (e.g.

timer and inputs) is possible, but a transition from wait

mode to run mode is only possible as described above.

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SAA1305T/N1,112

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NXP Semiconductors

Description:

Encoders, Decoders, Multiplexers & Demultiplexers ANALOG AUDIO MISC

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