DS2431P+ Datasheet DS2431+, DS2431X-S+, DS2431GB+T | P4-P6

Note 19: Current drawn from IO during the EEPROM programming interval. The pullup circuit on IO during the programming interval

should be such that the voltage at IO is greater than or equal to V

PUPMIN

. If V

PUP

in the system is close to V

PUPMIN

, a low-

impedance bypass of R

PUP

, which can be activated during programming, may need to be added.

Note 20: Interval begins t

REHMAX

after the trailing rising edge on IO for the last time slot of the E/S byte for a valid Copy Scratchpad

sequence. Interval ends once the device’s self-timed EEPROM programming cycle is complete and the current drawn by

the device has returned from I

PROG

to I

Note 21: t

PROG

for units branded version “A1” is 12.5ms. t

PROG

for units branded version “A2” and later is 10ms.

Note 22: Write-cycle endurance is degraded as T

increases.

Note 23: Not 100% production tested; guaranteed by reliability monitor sampling.

Note 24: Data retention is degraded as T

increases.

Note 25: Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to the

data sheet limit at operating temperature range is established by reliability testing.

Note 26: EEPROM writes can become nonfunctional after the data-retention time is exceeded. Long-term storage at elevated tem-

peratures is not recommended; the device can lose its write capability after 10 years at +125°C or 40 years at +85°C.

COMPARISON TABLE

LEGACY VALUES DS2431 VALUES

STANDARD SPEED

(μs)

OVERDRIVE SPEED

(μs)

STANDARD SPEED

(μs)

OVERDRIVE SPEED

(μs)

PARAMETER

MIN MAX MIN MAX MIN MAX MIN MAX

SLOT

(including t

REC

) 61 (undefined) 7 (undefined) 65* (undefined) 8* (undefined)

RSTL

480 (undefined) 48 80 480 640 48 80

PDH

15 60 2 6 15 60 2 6

PDL

60 240 8 24 60 240 8 24

W0L

60 120 6 16 60 120 6 15.5

1024-Bit, 1-Wire EEPROM

DS2431

4 Maxim Integrated

Intentional change; longer recovery time requirement due to modified 1-Wire front-end.

Note: Numbers in bold are not in compliance with legacy 1-Wire product standards.

Pin Description

TSOC TO-92 TDFN-EP SFN UCSPR

NAME FUNCTION

3, 4, 5, 6 3 1, 4, 5, 6 —

A2, A3, C2,

N.C. Not Connected

2 2 2 1 C1 IO

1-Wire Bus Interface. Open-drain signal

that requires an external pullup resistor.

1 1 3 2 A1 GND Ground Reference

— — — — — EP

Exposed Pad (TDFN only). Solder

evenly to the board’s ground plane for

proper operation. Refer to Application

Note 3273: Exposed Pads: A Brief

Introduction for additional information.

1024-Bit, 1-Wire EEPROM

DS2431

Maxim Integrated 5

Detailed Description

The DS2431 combines 1024 bits of EEPROM, an

8-byte register/control page with up to 7 user read/write

bytes, and a fully featured 1-Wire interface in a single

chip. Each DS2431 has its own 64-bit ROM registration

number that is factory lasered into the chip to provide a

guaranteed unique identity for absolute traceability.

Data is transferred serially through the

1-Wire protocol, which requires only a single data lead

and a ground return. The DS2431 has an additional

memory area called the scratchpad that acts as a

buffer when writing to the main memory or the register

page. Data is first written to the scratchpad from which

it can be read back. After the data has been verified, a

Copy Scratchpad command transfers the data to its

final memory location. The DS2431 applications include

accessory/PCB identification, medical sensor calibra-

tion data storage, analog sensor calibration including

IEEE P1451.4 smart sensors, ink and toner print car-

tridge identification, and after-market management of

consumables.

Overview

The block diagram in Figure 1 shows the relationships

between the major control and memory sections of the

DS2431. The DS2431 has four main data components:

64-bit lasered ROM, 64-bit scratchpad, four 32-byte

pages of EEPROM, and a 64-bit register page.

MEMORY

FUNCTION

CONTROL UNIT

DATA MEMORY

4 PAGES OF

256 BITS EACH

CRC-16

GENERATOR

64-BIT

SCRATCHPAD

1-Wire

FUNCTION CONTROL

64-BIT

LASERED ROM

PARASITE POWER

64 BITS

DS2431

Figure 1. Block Diagram

1024-Bit, 1-Wire EEPROM

DS2431

6 Maxim Integrated

The hierarchical structure of the 1-Wire protocol is

shown in Figure 2. The bus master must first provide

one of the seven ROM function commands: Read ROM,

Match ROM, Search ROM, Skip ROM, Resume,

Overdrive-Skip ROM, or Overdrive-Match ROM. Upon

completion of an Overdrive-Skip ROM or Overdrive-

Match ROM command byte executed at standard

speed, the device enters overdrive mode where all

subsequent communication occurs at a higher speed.

The protocol required for these ROM function com-

mands is described in Figure 9. After a ROM function

command is successfully executed, the memory func-

tions become accessible and the master can provide

any one of the four memory function commands. The

protocol for these memory function commands is

described in Figure 7. All data is read and written

least significant bit first.

64-Bit Lasered ROM

Each DS2431 contains a unique ROM code that is 64

bits long. The first 8 bits are a 1-Wire family code. The

next 48 bits are a unique serial number. The last 8 bits

are a cyclic redundancy check (CRC) of the first 56 bits.

See Figure 3 for details. The 1-Wire CRC is generated

using a polynomial generator consisting of a shift regis-

ter and XOR gates as shown in Figure 4. The polynomial

is X

+ X

+ 1. Additional information about the

1-Wire CRC is available in Application Note 27:

Understanding and Using Cyclic Redundancy Checks

with Maxim i

Button

Products

The shift register bits are initialized to 0. Then, starting

with the least significant bit of the family code, one bit

at a time is shifted in. After the 8th bit of the family code

has been entered, the serial number is entered. After

the last bit of the serial number has been entered, the

shift register contains the CRC value. Shifting in the 8

bits of the CRC returns the shift register to all 0s.

DS2431 COMMAND LEVEL:

AVAILABLE COMMANDS: DATA FIELD AFFECTED:

READ ROM

MATCH ROM

SEARCH ROM

SKIP ROM

RESUME

OVERDRIVE-SKIP ROM

OVERDRIVE-MATCH ROM

64-BIT REG. #, RC-FLAG

RC-FLAG

RC-FLAG, OD-FLAG

64-BIT REG. #, RC-FLAG, OD-FLAG

1-Wire ROM FUNCTION COMMANDS

(SEE FIGURE 9)

WRITE SCRATCHPAD

READ SCRATCHPAD

COPY SCRATCHPAD

READ MEMORY

64-BIT SCRATCHPAD, FLAGS

64-BIT SCRATCHPAD

DATA MEMORY, REGISTER PAGE

DS2431-SPECIFIC

MEMORY FUNCTION COMMANDS

(SEE FIGURE 7)

Figure 2. Hierarchical Structure for 1-Wire Protocol

MSB

8-BIT

CRC CODE

48-BIT SERIAL NUMBER

MSB MSBLSB

LSB

8-BIT FAMILY CODE

(2Dh)

MSBLSB

Figure 3. 64-Bit Lasered ROM

Button is a registered trademark of Maxim Integrated Products, Inc.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27

DS2431P+

Mfr. #:

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Description:

EEPROM 1024-Bit 1-Wire EEPROM

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