DS2431P+ Datasheet DS2431+, DS2431X-S+, DS2431GB+T | P7-P9

1024-Bit, 1-Wire EEPROM

DS2431

Maxim Integrated 7

Memory Access

Data memory and registers are located in a linear

address space, as shown in Figure 5. The data memo-

ry and the registers have unrestricted read access.

The DS2431 EEPROM array consists of 18 rows of 8

bytes each. The first 16 rows are divided equally into

four memory pages (32 bytes each). These four pages

are the primary data memory. Each page can be indi-

vidually set to open (unprotected), write protected, or

EPROM mode by setting the associated protection

byte in the register row. As a factory default, the entire

data memory is unprotected and its contents are unde-

fined. The last two rows contain protection registers

and reserved bytes. The register row consists of 4 pro-

tection control bytes, a copy-protection byte, the facto-

ry byte, and 2 user byte/manufacture ID bytes. The

manufacturer ID can be a customer-supplied identifi-

cation code that assists the application software in

identifying the product the DS2431 is associated with.

1ST

STAGE

2ND

STAGE

3RD

STAGE

4TH

STAGE

7TH

STAGE

8TH

STAGE

6TH

STAGE

5TH

STAGE

POLYNOMIAL = X

+ X

+ 1

INPUT DATA

Figure 4. 1-Wire CRC Generator

ADDRESS RANGE TYPE DESCRIPTION PROTECTION CODES

0000h to 001Fh R/(W) Data Memory Page 0 —

0020h to 003Fh R/(W) Data Memory Page 1 —

0040h to 005Fh R/(W) Data Memory Page 2 —

0060h to 007Fh R/(W) Data Memory Page 3 —

0080h* R/(W) Protection Control Byte Page 0

55h: Write Protect P0; AAh: EPROM Mode P0;

55h or AAh: Write Protect 80h

0081h* R/(W) Protection Control Byte Page 1

55h: Write Protect P1; AAh: EPROM Mode P1;

55h or AAh: Write Protect 81h

0082h* R/(W) Protection Control Byte Page 2

55h: Write Protect P2; AAh: EPROM Mode P2;

55h or AAh: Write Protect 82h

0083h* R/(W) Protection Control Byte Page 3

55h: Write Protect P3; AAh: EPROM Mode P3;

55h or AAh: Write Protect 83h

0084h* R/(W) Copy Protection Byte

55h or AAh: Copy Protect 0080h:008Fh, and Any

Write-Protected Pages

0085h R Factory Byte. Set at Factory.

AAh: Write Protect 85h, 86h, 87h;

55h: Write Protect 85h; Unprotect 86h, 87h

0086h R/(W) User Byte/Manufacturer ID —

0087h R/(W) User Byte/Manufacturer ID —

0088h to 008Fh — Reserved —

Figure 5. Memory Map

Once programmed to AAh or 55h this address becomes read only. All other codes can be stored, but neither write protect the

address nor activate any function.

1024-Bit, 1-Wire EEPROM

DS2431

8 Maxim Integrated

Contact the factory to set up and register a custom

manufacturer ID. The last row is reserved for future

use. It is undefined in terms of R/W functionality and

should not be used.

In addition to the main EEPROM array, an 8-byte

volatile scratchpad is included. Writes to the EEPROM

array are a two-step process. First, data is written to the

scratchpad and then copied into the main array. This

allows the user to first verify the data written to the

scratchpad prior to copying into the main array. The

device only supports full row (8-byte) copy operations.

For data in the scratchpad to be valid for a copy opera-

tion, the address supplied with a Write Scratchpad

command must start on a row boundary, and 8 full

bytes must be written into the scratchpad.

The protection control registers determine how incom-

ing data on a Write Scratchpad command is loaded

into the scratchpad. A protection setting of 55h (write

protect) causes the incoming data to be ignored and

the target address main memory data to be loaded into

the scratchpad. A protection setting of AAh (EPROM

mode) causes the logical AND of incoming data and

target address main memory data to be loaded into the

scratchpad. Any other protection control register set-

ting leaves the associated memory page open for unre-

stricted write access. Note: For the EPROM mode to

function, the entire affected memory page must first be

programmed to FFh. Protection-control byte settings of

55h or AAh also write protect the protection-control

byte. The protection-control byte setting of 55h does

not block the copy. This allows write-protected data to

be refreshed (i.e., reprogrammed with the current data)

in the device.

The copy-protection byte is used for a higher level of

security and should only be used after all other protec-

tion control bytes, user bytes, and write-protected

pages are set to their final value. If the copy-protection

byte is set to 55h or AAh, all copy attempts to the regis-

ter row and user-byte row are blocked. In addition, all

copy attempts to write-protected main memory pages

(i.e., refresh) are blocked.

Address Registers and Transfer Status

The DS2431 employs three address registers: TA1,

TA2, and E/S (Figure 6). These registers are common to

many other 1-Wire devices but operate slightly differ-

ently with the DS2431. Registers TA1 and TA2 must be

loaded with the target address to which the data is writ-

ten or from which data is read. Register E/S is a read-

only transfer-status register used to verify data integrity

with write commands. E/S bits E[2:0] are loaded with

the incoming T[2:0] on a Write Scratchpad command

and increment on each subsequent data byte. This is,

in effect, a byte-ending offset counter within the 8-byte

scratchpad. Bit 5 of the E/S register, called PF, is a

logic 1 if the data in the scratchpad is not valid due to a

loss of power or if the master sends fewer bytes than

needed to reach the end of the scratchpad. For a valid

write to the scratchpad, T[2:0] must be 0 and the mas-

ter must have sent 8 data bytes. Bits 3, 4, and 6 have

no function; they always read 0. The highest valued bit

of the E/S register, called authorization accepted (AA),

acts as a flag to indicate that the data stored in the

scratchpad has already been copied to the target

memory address. Writing data to the scratchpad clears

this flag.

BIT # 7 6 5 4 3 2 1 0

TARGET ADDRESS (TA1) T7 T6 T5 T4 T3 T2 T1 T0

TARGET ADDRESS (TA2) T15 T14 T13 T12 T11 T10 T9 T8

ENDING ADDRESS WITH

DATA STATUS (E/S)

(READ ONLY)

AA 0 PF 0 0 E2 E1 E0

Figure 6. Address Registers

1024-Bit, 1-Wire EEPROM

DS2431

Maxim Integrated 9

Writing with Verification

To write data to the DS2431, the scratchpad must be

used as intermediate storage. First, the master issues

the Write Scratchpad command to specify the desired

target address, followed by the data to be written to the

scratchpad. Note that Copy Scratchpad commands

must be performed on 8-byte boundaries, i.e., the three

LSBs of the target address (T2, T1, T0) must be equal

to 000b. If T[2:0] are sent with nonzero values, the copy

function is blocked. Under certain conditions (see the

Write Scratchpad [0Fh]

section) the master receives an

inverted CRC-16 of the command, address (actual

address sent), and data at the end of the Write

Scratchpad command sequence. Knowing this CRC

value, the master can compare it to the value it has cal-

culated to decide if the communication was successful

and proceed to the Copy Scratchpad command. If the

master could not receive the CRC-16, it should send

the Read Scratchpad command to verify data integrity.

As a preamble to the scratchpad data, the DS2431

repeats the target address TA1 and TA2 and sends the

contents of the E/S register. If the PF flag is set, data

did not arrive correctly in the scratchpad, or there was

a loss of power since data was last written to the

scratchpad. The master does not need to continue

reading; it can start a new trial to write data to the

scratchpad. Similarly, a set AA flag together with a

cleared PF flag indicates that the device did not recog-

nize the Write command.

If everything went correctly, both flags are cleared.

Now the master can continue reading and verifying

every data byte. After the master has verified the data,

it can send the Copy Scratchpad command, for exam-

ple. This command must be followed exactly by the

data of the three address registers, TA1, TA2, and E/S.

The master should obtain the contents of these regis-

ters by reading the scratchpad.

Memory Function Commands

The

Memory Function Flowchart

(Figure 7) describes

the protocols necessary for accessing the memory of

the DS2431. An example on how to use these functions

to write to and read from the device is in the

Memory

Function Example

section. The communication

between the master and the DS2431 takes place either

at standard speed (default, OD = 0) or at overdrive

speed (OD = 1). If not explicitly set into overdrive

mode, the DS2431 assumes standard speed.

Write Scratchpad [0Fh]

The Write Scratchpad command applies to the data

memory and the writable addresses in the register

page. For the scratchpad data to be valid for copying

to the array, the user must perform a Write Scratchpad

command of 8 bytes starting at a valid row boundary.

The Write Scratchpad command accepts invalid

addresses and partial rows, but subsequent Copy

Scratchpad commands are blocked.

After issuing the Write Scratchpad command, the mas-

ter must first provide the 2-byte target address, fol-

lowed by the data to be written to the scratchpad. The

data is written to the scratchpad starting at the byte off-

set of T[2:0]. The E/S bits E[2:0] are loaded with the

starting byte offset and increment with each subse-

quent byte. Effectively, E[2:0] is the byte offset of the

last full byte written to the scratchpad. Only full data

bytes are accepted.

When executing the Write Scratchpad command, the

CRC generator inside the DS2431 (Figure 13) calcu-

lates a CRC of the entire data stream, starting at the

command code and ending at the last data byte as

sent by the master. This CRC is generated using the

CRC-16 polynomial by first clearing the CRC generator

and then shifting in the command code (0Fh) of the

Write Scratchpad command, the target addresses (TA1

and TA2), and all the data bytes. Note that the CRC-16

calculation is performed with the actual TA1 and TA2

and data sent by the master. The master can end the

Write Scratchpad command at any time. However, if

the end of the scratchpad is reached (E[2:0] = 111b),

the master can send 16 read time slots and receive the

CRC generated by the DS2431.

If a Write Scratchpad command is attempted to a write-

protected location, the scratchpad is loaded with the

data already existing in memory rather than the data

transmitted. Similarly, if the target address page is in

EPROM mode, the scratchpad is loaded with the bit-

wise logical AND of the transmitted data and data

already existing in memory.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27

DS2431P+

Mfr. #:

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Maxim Integrated

Description:

EEPROM 1024-Bit 1-Wire EEPROM

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DS2431P+

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