74LVT573 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 8 — 22 November 2011 6 of 17
NXP Semiconductors
74LVT573
3.3 V octal D-type transparent latch; 3-state
[1] Typical values are measured at V
CC
= 3.3 V and T
amb
= 25 C.
[2] For valid test results, data must not be loaded into the flip-flops (or latches) after applying power.
[3] Unused pins at V
CC
or GND.
[4] This is the bus hold overdrive current required to force the input to the opposite logic state.
[5] This parameter is valid for any V
CC
between 0 V and 1.2 V with a transition time of up to 10 ms. From V
CC
= 1.2 V to V
CC
=3.3 V 0.3 V
a transition time of 100 s is permitted. This parameter is valid for T
amb
=25C only.
[6] I
CC
is measured with outputs pulled to V
CC
or GND.
[7] This is the increase in supply current for each input at the specified voltage level other than V
CC
or GND.
I
I
input leakage current all input pins;
V
CC
= 0 V or 3.6 V; V
I
=5.5V - 1 10 A
control pins;
V
CC
= 3.6 V; V
CC
or GND - 0.1 1 A
data pins
V
CC
= 3.6 V; V
I
=V
CC
[3]
-0.11A
V
CC
= 3.6 V; V
I
=0V 5 1-A
I
OFF
power-off leakage current V
CC
= 0 V; V
I
or V
O
= 0 V to 4.5 V - 1 100 A
I
BHL
bus hold LOW current Dn input; V
CC
= 3 V; V
I
=0.8V
[4]
75 150 - A
I
BHH
bus hold HIGH current Dn input; V
CC
= 3 V; V
I
=2.0V - 150 75 A
I
BHHO
bus hold HIGH overdrive current Dn input; V
CC
= 3.6; V
I
= 0 V to
3.6 V
[4]
--500A
I
BHLO
bus hold LOW overdrive current Dn input; V
CC
= 3.6; V
I
= 0 V to
3.6 V
500 - - A
I
LO
output leakage current Qn output HIGH when
V
O
= 5.5 V and V
CC
=3.0V
-60125A
I
O(pu/pd)
power-up/power-down
output current
V
CC
1.2 V; V
O
=0.5Vto V
CC
;
V
I
=GNDorV
CC
; OE = don’t care
[5]
-1100 A
I
OZ
OFF-state output current V
CC
= 3.6 V; V
I
=V
IH
or V
IL
output HIGH: V
O
=3.0V - 1 5 A
output LOW: V
O
=0.5V 5 1-A
I
CC
supply current V
CC
= 3.6 V; V
I
=GNDorV
CC
;
I
O
=0A
outputs HIGH - 0.13 0.19 mA
outputs LOW - 3 12 mA
outputs disabled
[6]
- 0.13 0.19 mA
I
CC
additional supply current per input pin; V
CC
= 3 V to 3.6 V;
one input at V
CC
0.6 V and other
inputs at V
CC
or GND
[7]
-0.10.2mA
C
I
input capacitance V
I
= 0 V or 3.0 V - 4 - pF
C
O
output capacitance outputs disabled; V
O
= 0 V or 3.0 V - 8 - pF
Table 6. Static characteristics
…continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions T
amb
= 40 C to +85 C Unit
Min Typ
[1]
Max
74LVT573 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 8 — 22 November 2011 7 of 17
NXP Semiconductors
74LVT573
3.3 V octal D-type transparent latch; 3-state
10. Dynamic characteristics
[1] Typical values are at V
CC
= 3.3 V and T
amb
=25 C.
[2] t
su
is the same as t
su(L)
and t
su(H)
.
[3] t
h
is the same as t
h(L)
and t
h(H)
.
[4] t
W
is the same as t
WL
and t
WH
.
Table 7. Dynamic characteristics
Voltages are referenced to ground (GND = 0 V); for test circuit see Figure 11.
Symbol Parameter Conditions T
amb
= 40 C to +85 C Unit
Min Typ
[1]
Max
t
PLH
LOW to HIGH
propagation delay
LE to Qn; see Figure 6
V
CC
= 3.0 V to 3.6 V 1.6 3.5 5.6 ns
V
CC
= 2.7 V - - 6.3 ns
Dn to Qn; see Figure 7
V
CC
= 3.0 V to 3.6 V 1.0 2.5 4.2 ns
V
CC
= 2.7 V - - 4.7 ns
t
PHL
HIGH to LOW
propagation delay
LE to Qn; see Figure 6
V
CC
= 3.0 V to 3.6 V 2.5 4.3 6.5 ns
V
CC
= 2.7 V - - 7.2 ns
Dn to Qn; see Figure 7
V
CC
= 3.0 V to 3.6 V 1.0 2.7 4.3 ns
V
CC
= 2.7 V - - 5.2 ns
t
PZH
OFF-state to HIGH
propagation delay
OE to Qn; see Figure 8
V
CC
= 3.0 V to 3.6 V 1.0 2.8 5.1 ns
V
CC
= 2.7 V - - 6.2 ns
t
PZL
OFF-state to LOW
propagation delay
OE to Qn; see Figure 9
V
CC
= 3.0 V to 3.6 V 1.3 3.3 5.5 ns
V
CC
= 2.7 V - - 6.6 ns
t
PHZ
HIGH to OFF-state
propagation delay
OE to Qn; see Figure 8
V
CC
= 3.0 V to 3.6 V 2.0 3.7 5.7 ns
V
CC
= 2.7 V - - 6.7 ns
t
PLZ
LOW to OFF-state
propagation delay
OE to Qn; see Figure 9
V
CC
= 3.0 V to 3.6 V 1.5 3.0 4.6 ns
V
CC
= 2.7 V - - 5.1 ns
t
su
set-up time Dn to LE; see Figure 10
[2]
V
CC
= 3.0 V to 3.6 V 0.7 - - ns
V
CC
=2.7V 0.6 - - ns
t
h
hold time Dn to LE; see Figure 10
[3]
V
CC
= 3.0 V to 3.6 V 1.6 - - ns
V
CC
=2.7V 1.8 - - ns
t
W
pulse width LE input HIGH; see Figure 6
[4]
V
CC
= 3.0 V to 3.6 V 3.3 - - ns
V
CC
=2.7V 3.3 - - ns
74LVT573 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 8 — 22 November 2011 8 of 17
NXP Semiconductors
74LVT573
3.3 V octal D-type transparent latch; 3-state
11. Waveforms
Measurement points are given in Table 8. Measurement points are given in Table 8.
Fig 6. Propagation delays latch enable input (LE) to
output (Qn), and latch enable (LE) pulse width
Fig 7. Propagation delay data input (Dn) to
output (Qn)
Measurement points are given in Table 8.
V
OL
and V
OH
are typical voltage output levels that occur
with the output load.
Measurement points are given in Table 8
.
Fig 8. Output enable time to HIGH-state and output
disable time from HIGH-state
Fig 9. Output enable time to LOW-state and output
disable time from LOW-state
Measurement points are given in Table 8.
Remark: The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig 10. Data setup and hold times for data (Dn) and latch enable (LE) inputs
001aai743
LE
input
Qn
output
t
PHL
t
PLH
t
WH
V
M
V
OH
V
I
0 V
V
OL
V
M
t
WL
001aai742
Dn input
Qn output
t
PHL
t
PLH
0 V
V
I
V
M
V
M
V
OH
V
OL
Qn output
001aai745
OE input
V
M
V
I
V
OH
0 V
0 V
t
PZH
t
PHZ
V
Y
V
M
V
M
001aai746
t
PZL
t
PLZ
V
M
V
M
V
M
Qn output
OE input
V
I
V
OL
3.0 V
V
X
0 V
001aai744
t
h(L)
t
su(L)
t
h(H)
t
su(H)
V
M
V
M
V
I
0 V
V
I
0 V
LE input
Dn input
Table 8. Measurement points
Input Output
V
M
V
M
V
X
V
Y
1.5V 1.5V V
OL
+ 0.3 V V
OH
0.3 V

74LVT573D,112

Mfr. #:
Manufacturer:
Nexperia
Description:
Latches 3.3V OCTAL D TRANS
Lifecycle:
New from this manufacturer.
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