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9DB233AGILFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
9DB233
TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3
IDT®
TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3 4
9DB233 OCTOBER 20, 2016
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9DB233. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over
the recommended operating temperature range.
Electrical Characteristics–DIF_IN Clock Input Parameters
Electrical Characteristics–Current Consumption
PARAMETER SYMBOL CONDITIONS
MIN TYP MAX
UNITS NOTES
3.3V Core Supply Voltage VDDA 4.6 V 1,2
3.3V Logic Supply Voltage VDD 4.6 V
1,2
Input Low Voltage V
IL
GND-0.5 V 1
Input High Voltage V
IH
Except for SMBus interface V
DD
+0.5V V 1
Input High Voltage V
IHSMB
SMBus clock and data pins 5.5V V 1
Storage Temperature Ts -65 150
°
C
1
Junction Temperature Tj 125 °C
1
Input ESD protection
ESD prot Human Body Model 2000 V 1
1
Guaranteed by design and characterization, not 100% tested in production.
2
Operation under these conditions is neither implied nor
g
uaranteed.
T
AMB
=T
COM
or T
IND
unless otherwise indicated, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Input Crossover Voltage -
DIF_IN
V
CROSS
Cross Over Voltage 150 375 900 mV 1
Input Swing - DIF_IN V
SWING
Differential value 300 mV 1
Input Slew Rate - DIF_IN dv/dt Measured differentially 1 8 V/ns 1,2
Input Leakage Current I
IN
V
IN
= V
DD ,
V
IN
=
GND -5 5 uA
Input Duty Cycle d
tin
Measurement from differential wavefrom 45 55 % 1
Input Jitter - Cycle to Cycle J
DIFIn
Differential Measurement 0 125 ps 1
1
Guaranteed by design and characterization, not 100% tested in production.
2
Slew rate measured throu
g
h +/-75mV window centered around differential zero
DD3.3OP
L
DD3.3PD
Guaranteed by desi
g
n and characterization, not 100% tested in production.
9DB233
TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3
IDT®
TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3 5
9DB233 OCTOBER 20, 2016
Electrical Characteristics–Input/Supply/Common Parameters
TA = T
COM
or T
IND;
Supply Voltage VDD = 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
T
COM
Commmercial range 0 70 °C 1
T
IND
Industrial range -40 85 °C 1
Input High Voltage V
IH
Single-ended inputs, except SMBus, low
threshold and tri-level inputs
2V
DD
+ 0.3 V 1
Input Low Voltage V
IL
Single-ended inputs, except SMBus, low
threshold and tri-level inputs
GND
- 0.3 0.8 V 1
I
IN
Single-ended inputs, V
IN
= GND, V
IN
= VDD -5 5 uA 1
I
INP
Single-ended inputs
V
IN
= 0 V; Inputs with internal pull-up resistors
V
IN
= VDD; Inputs with internal pull-down resistors
-200 200 uA 1
F
ib
yp
V
DD
= 3.3 V, Bypass mode 10 110 MHz 2
F
i
p
ll
V
DD
= 3.3 V, 100MHz PLL mode 33 100.00 110 MHz 2
Pin Inductance L
p
in
7nH1
C
IN
Logic Inputs, except DIF_IN 1.5 5 pF 1
C
INDIF_IN
DIF_IN differential clock inputs 1.5 2.7 pF 1,4
C
OUT
Output pin capacitance 6 pF 1
Clk Stabilization T
STAB
From V
DD
Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
0.800 1.8 ms 1,2
Input SS Modulation
Frequency
f
MODIN
Allowable Frequency
(Triangular Modulation)
30 33 kHz 1
OE# Latency t
LATOE#
DIF start after OE# assertion
DIF stop after OE# deassertion
1 3 cycles 1,3
Tdrive_PD# t
DRVPD
DIF output enable after
PD# de-assertion
300 us 1,3
Tfall t
F
Fall time of control inputs 5 ns 1,2
Trise t
R
Rise time of control inputs 5 ns 1,2
SMBus Input Low Voltage V
ILSMB
0.8 V 1
SMBus Input High Voltage V
IHSMB
2.1 V
DDSMB
V1
SMBus Output Low Voltage V
OLSMB
@ I
PULLUP
0.4 V 1
SMBus Sink Current I
PULLUP
@ V
OL
4mA1
Nominal Bus Voltage V
DDSMB
3V to 5V +/- 10% 2.7 5.5 V 1
SCLK/SDATA Rise Time t
RSMB
(Max VIL - 0.15) to (Min VIH + 0.15) 1000 ns 1
SCLK/SDATA Fall Time t
FSMB
(Min VIH + 0.15) to (Max VIL - 0.15) 300 ns 1
SMBus Operating
Frequency
f
MAXSMB
Maximum SMBus operating frequency 100 kHz 1,5
1
Guaranteed by desi
g
n and characterization, not 100% tested in production.
2
Control input must be monotonic from 20% to 80% of input swin
g
.
5
The differential input clock must be running for the SMBus to be active
Ambient Operating
Temperature
Input Current
3
Time from deassertion until out
p
uts are >200 mV
4
DIF_IN input
Capacitance
Input Frequency
9DB233
TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3
IDT®
TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3 6
9DB233 OCTOBER 20, 2016
Electrical Characteristics–DIF 0.7V Current Mode Differential Outputs
Electrical Characteristics–Output Duty Cycle, Jitter, Skew and PLL Characteristics
T
A
= T
COM
or T
IND;
Supply Voltage VDD = 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Slew rate Trf Scope avera
g
in
g
on 0.6 2 4
V/ns
1, 2, 3
Slew rate matching
∆
Trf Slew rate matching, Scope averaging on 4.2 20
%
1, 2, 4
Voltage High VHigh 660 791 850 1
Voltage Low VLow -150 13 150 1
Max Voltage Vmax 801 1150 1
Min Voltage Vmin -300 5 1
Vswin
g
Vswin
g
Scope avera
g
in
g
off 300 1557 mV 1, 2
Crossing Voltage (abs) Vcross_abs Scope averaging off 250 367 550 mV 1, 5
Crossing Voltage (var)
∆
-Vcross Scope averaging off 46 140 mV 1, 6
2
Measured from differential waveform
6
The total variation of all Vcross measurements in any particular system. Note that this is a subset of V_cross_min/max (V_cross
absolute
)
allowed. The intent is to limit Vcross induced modulation b
y
settin
g
V_cross_delta to be smaller than V_cross absolute.
mV
Statistical measurement on single-ended signal
using oscilloscope math function. (Scope
averaging on)
Measurement on single ended signal using
absolute value. (Scope averaging off)
mV
1
Guaranteed by design and characterization, not 100% tested in production. IREF = VDD/(3xR
R
). For R
R
= 475
Ω
(1%), I
REF
= 2.32mA.
I
OH
= 6 x I
REF
and V
OH
= 0.7V @ Z
O
=50
Ω
(100
Ω
differential impedance).
3
Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4
Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on
the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5
Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
TA = T
COM
or T
IND;
Supply Voltage VDD = 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
-3dB point in Hi
g
h BW Mode 2 2.2 4 MHz 1
-3dB point in Low BW Mode 0.4 0.5 1 MHz 1
PLL Jitter Peaking t
JPEAK
Peak Pass band Gain 0.6 1.5 dB 1
Duty Cycle t
D
C
Measured differentially, PLL Mode 45 48 55 % 1
Duty Cycle Distortion t
DCD
Measured differentially, Bypass Mode @100MHz -2 0.4 2 % 1,4
t
p
dBYP
Bypass Mode, V
T
= 50% 2500 3660 4500 ps 1
t
p
dPLL
Hi BW PLL Mode V
T
= 50% -50 136 350 ps 1
Skew, Output to Output t
sk3
V
T
= 50% 16 50 ps 1
PLL mode 29 50 ps 1,3
Additive Jitter in Bypass Mode 0.2 50 ps 1,3
1
Guaranteed by design and characterization, not 100% tested in production.
2
I
RE
F
= V
DD
/(3xR
R
). For R
R
= 475
Ω
(1%), I
RE
F
= 2.32mA. I
OH
= 6 x I
RE
F
and V
OH
= 0.7V @ Z
O
=50
Ω
.
3
Measured from differential waveform
4
Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.
Skew, Input to Output
Jitter, Cycle to cycle t
jcyc-cyc
PLL Bandwidth BW
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

9DB233AGILFT

Mfr. #:
Buy 9DB233AGILFT
Manufacturer:
IDT
Description:
Clock Buffer 2-output 3.3 V PCIe Gen1-2-3 Zero Delay / Fanout Buffer
Lifecycle:
New from this manufacturer.
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