Specifications ispLSI 2128VE
5
USE 2128VE-250
FOR NEW DESIGNS
External Timing Parameters
Over Recommended Operating Conditions
t
pd1
UNITS
TEST
COND.
1. Unless noted otherwise, all parameters use a GRP load of four, 20 PTXOR path, ORP and Y0 clock.
2. Standard 16-bit counter using GRP feedback.
3. Reference Switching Test Conditions section.
Table 2-0030A/2128VE
v.1.0
1
3
2
1
tsu2 + tco1
( )
DESCRIPTION#PARAMETER
A1Data Propagation Delay, 4PT Bypass, ORP Bypass ns
t
pd2
A2Data Propagation Delay ns
f
max
A3Clock Frequency with Internal Feedback MHz
f
max (Ext.)
–4Clock Frequency with External Feedback MHz
f
max (Tog.)
–5Clock Frequency, Max. Toggle MHz
t
su1
–6GLB Reg. Setup Time before Clock, 4 PT Bypass ns
t
co1
A7GLB Reg. Clock to Output Delay, ORP Bypass ns
t
h1
–8GLB Reg. Hold Time after Clock, 4 PT Bypass ns
t
su2
–9GLB Reg. Setup Time before Clock ns
t
co2
A10GLB Reg. Clock to Output Delay ns
t
h2
–11GLB Reg. Hold Time after Clock ns
t
r1
A12Ext. Reset Pin to Output Delay, ORP Bypass ns
t
rw1
–13Ext. Reset Pulse Duration ns
t
ptoeen
B14Input to Output Enable ns
t
ptoedis
C15Input to Output Disable ns
t
goeen
B16Global OE Output Enable ns
t
goedis
C17Global OE Output Disable ns
t
wh
–18External Synchronous Clock Pulse Duration, High ns
t
wl
–19External Synchronous Clock Pulse Duration, Low ns
-180
MIN. MAX.
– 5.0
–
180 –
–
–
–
–
0.0
4.5
–
0.0
–
4.0
–
–
–
–
2.5 –
2.5 –
125
200
3.5
3.5
–
–
4.5
–
7.0
–
10.0
10.0
5.0
5.0
7.5
-250
MIN. MAX.
– 4.0
–
250 –
–
–
–
–
0.0
3.3
–
0.0
–
3.5
–
–
–
–
1.8 –
1.8 –
158
277
2.5
3.0
–
–
3.7
–
6.0
–
6.0
6.0
4.0
4.0
6.0
