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ISPLSI 2128VE-250LQ160

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
Specifications ispLSI 2128VE
7
USE 2128VE-250 FOR NEW DESIGNS
Internal Timing Parameters
1
Over Recommended Operating Conditions
tio
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
Table 2-0036A/2128VE
v.1.0
Inputs
UNITS
DESCRIPTION#
2
PARAMETER
20 Input Buffer Delay ns
tdin
21 Dedicated Input Delay ns
tgrp
22 GRP Delay ns
GLB
t1ptxor
25 1 Product Term/XOR Path Delay ns
t20ptxor
26 20 Product Term/XOR Path Delay ns
txoradj
27 XOR Adjacent Path Delay ns
tgbp
28 GLB Register Bypass Delay ns
tgsu
29 GLB Register Setup Time before Clock ns
tgh
30 GLB Register Hold Time after Clock ns
tgco
31 GLB Register Clock to Output Delay ns
3
tgro
32 GLB Register Reset to Output Delay ns
tptre
33 GLB Product Term Reset to Register Delay ns
tptoe
34 GLB Product Term Output Enable to I/O Cell Delay ns
tptck
35 GLB Product Term Clock Delay ns
ORP
tob
38 Output Buffer Delay ns
tsl
39 Output Slew Limited Delay Adder ns
GRP
t4ptbpc
23 4 Product Term Bypass Path Delay (Combinatorial) ns
t4ptbpr
24 4 Product Term Bypass Path Delay (Registered) ns
torp
36 ORP Delay ns
torpbp
37 ORP Bypass Delay ns
Outputs
toen
40 I/O Cell OE to Output Enabled ns
todis
41 I/O Cell OE to Output Disabled ns
tgoe
42 Global Output Enable ns
tgy0
43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) ns
tgy1/2
44 Clock Delay, Y1 or Y2 to Global GLB Clock Line ns
Clocks
tgr
45 Global Reset to GLB
-180
MIN. MAX.
0.5
1.1
0.6
3.4
3.4
3.4
0.0
—
—
0.3
0.6
4.3
5.9
4.0
1.6
2.0
1.9
2.4
1.4
0.4
3.0
3.0
2.0
1.2
1.4
4.4
—
—
—
—
—
—
—
1.2
2.3
—
—
—
—
1.0
—
—
—
—
—
—
—
—
—
1.2
1.4
—
-250
MIN. MAX.
0.5
0.7
0.2
2.8
2.8
2.8
0.0
—
—
0.2
0.3
3.7
2.9
3.6
1.4
2.0
1.5
2.0
1.1
0.4
2.4
2.4
1.6
1.0
1.2
3.9
—
—
—
—
—
—
—
0.8
1.7
—
—
—
—
0.8
—
—
—
—
—
—
—
—
—
1.0
1.2
—ns
Global Reset
Specifications ispLSI 2128VE
8
Internal Timing Parameters
1
Over Recommended Operating Conditions
tio
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
Table 2-0036B/2128VE
v.1.0
Inputs
UNITS
DESCRIPTION#
2
PARAMETER
20 Input Buffer Delay ns
tdin
21 Dedicated Input Delay ns
tgrp
22 GRP Delay ns
GLB
t1ptxor
25 1 Product Term/XOR Path Delay ns
t20ptxor
26 20 Product Term/XOR Path Delay ns
txoradj
27 XOR Adjacent Path Delay ns
tgbp
28 GLB Register Bypass Delay ns
tgsu
29 GLB Register Setup Time before Clock ns
tgh
30 GLB Register Hold Time after Clock ns
tgco
31 GLB Register Clock to Output Delay ns
3
tgro
32 GLB Register Reset to Output Delay ns
tptre
33 GLB Product Term Reset to Register Delay ns
tptoe
34 GLB Product Term Output Enable to I/O Cell Delay ns
tptck
35 GLB Product Term Clock Delay ns
ORP
tob
38 Output Buffer Delay ns
tsl
39 Output Slew Limited Delay Adder ns
GRP
t4ptbpc
23 4 Product Term Bypass Path Delay (Combinatorial) ns
t4ptbpr
24 4 Product Term Bypass Path Delay (Registered) ns
torp
36 ORP Delay ns
torpbp
37 ORP Bypass Delay ns
Outputs
toen
40 I/O Cell OE to Output Enabled ns
todis
41 I/O Cell OE to Output Disabled ns
tgoe
42 Global Output Enable ns
tgy0
43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) ns
tgy1/2
44 Clock Delay, Y1 or Y2 to Global GLB Clock Line ns
Clocks
tgr
45 Global Reset to GLB ns
Global Reset
-135
MIN.
-100
MIN.MAX. MAX.
—
—
—
—
—
—
—
1.7
4.8
—
—
—
—
2.6
—
—
—
—
—
—
—
—
—
2.4
2.6
—
0.7
2.5
1.8
6.2
6.2
6.2
1.0
—
—
0.3
3.1
7.1
9.1
5.6
1.6
2.0
5.2
4.7
1.7
0.7
3.4
3.4
5.6
2.4
2.6
7.1
0.5
1.7
1.2
4.7
4.7
4.7
0.5
—
—
0.3
1.1
6.1
6.9
4.6
1.6
2.0
3.7
3.7
1.5
0.5
3.4
3.4
3.6
1.6
1.8
5.8
—
—
—
—
—
—
—
1.2
3.8
—
—
—
—
1.6
—
—
—
—
—
—
—
—
—
1.6
1.8
—
Specifications ispLSI 2128VE
9
ispLSI 2128VE Timing Model
GLB Reg
Delay
I/O Pin
(Output)
ORP
Delay
Feedback
Reg 4 PT Bypass
20 PT
XOR Delays
Control
PTs
I/O Pin
(Input)
Y0,1,2
GRP
GLB Reg Bypass ORP Bypass
DQ
RST
RE
OE
CK
I/O Delay
I/O CellORPGLBGRPI/O Cell
#24
#25, 26, 27
#33, 34,
35
#43, 44
#36
Reset
Ded. In
#21
#20
#28
#29, 30,
31, 32
#38,
39
GOE 0
#42
#40, 41
0491/2032
#22
Comb 4 PT Bypass #23
#37
#45
Derivations of
t
su,
t
h and
t
co from the Product Term Clock
=
=
=
=
t
su
2.8ns
Logic + Reg su - Clock (min)
(
t
io +
t
grp +
t
20ptxor) + (
t
gsu) - (
t
io +
t
grp +
t
ptck(min))
(#20 + #22 + #26) + (#29) - (#20 + #22 + #35)
(0.5 + 0.2 + 2.8) + (0.8) - (0.5 + 0.2 + 0.8)
=
=
=
=
t
hClock (max) + Reg h - Logic
(
t
io +
t
grp +
t
ptck(max)) + (
t
gh) - (
t
io +
t
grp +
t
20ptxor)
(#20 + #22 + #35) + (#30) - (#20 + #22 + #26)
(0.5 + 0.2 + 3.6) + (1.7) - (0.5 + 0.2 + 2.8)
=
=
=
=
t
co
Note: Calculations are based upon timing specifications for the ispLSI 2128VE-250L.
Clock (max) + Reg co + Output
(
t
io +
t
grp +
t
ptck(max)) + (
t
gco) + (
t
orp +
t
ob)
(#20 + #22 + #35) + (#31) + (#36 + #38)
(0.5 + 0.2 + 3.6) + (0.2) + (1.1 + 1.4)
Table 2-0042/2128VE
v.1.0
2.5ns
7.0ns
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

ISPLSI 2128VE-250LQ160

Mfr. #:
Buy ISPLSI 2128VE-250LQ160
Manufacturer:
Lattice
Description:
CPLD - Complex Programmable Logic Devices PROGRAMMABLE SUPER FAST HI DENSITY PLD
Lifecycle:
New from this manufacturer.
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