OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

AT42QT1070-SSUR

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P34
13
AT42QT1070 [DATASHEET]
9596C–AT42–05/2013
4. I
2
C Communications (Comms Mode Only)
4.1 I
2
C Protocol
4.1.1 Protocol
The I
2
C protocol is based around access to an address table (see Table 5-1 on page 15) and supports multibyte
reads and writes. The maximum clock rate is 400 kHz.
See Section A. on page 29 for an overview of I
2
C bus operation.
4.1.2 Signals
The I
2
C interface requires two signals to operate:
SDA - Serial Data
SCL - Serial Clock
A third line, CHANGE
, is used to signal when the device has seen a change in the status byte:
CHANGE
: Open-drain, active low when any capacitive key has changed state since the last I
2
C read. After reading
the two status bytes, this pin floats (high) again if it is pulled up with an external resistor. If the status bytes change
back to their original state before the host has read the status bytes (for example, a touch followed by a release), the
CHANGE
line is held low. In this case, a read to any memory location clears the CHANGE line.
4.2 I
2
C Address
There is one preset I
2
C address of 0x1B. This is not changeable.
4.3 Data Read/Write
4.3.1 Writing Data to the Device
The sequence of events required to write data to the device is shown next.
1. The host initiates the transfer by sending the START condition
2. The host follows this by sending the slave address of the device together with the WRITE bit.
3. The device sends an ACK.
Table 4-1. Description of Write Data Bits
Key Description
S START condition
SLA+W Slave address plus write bit
A Acknowledge bit
MemAddress Target memory address within device
Data Data to be written
P Stop condition
14
AT42QT1070 [DATASHEET]
9596C–AT42–05/2013
4. The host then sends the memory address within the device it wishes to write to.
5. The device sends an ACK if the write address is in the range 0x00 – 0x7F, otherwise it sends a NACK.
6. The host transmits one or more data bytes; each is acknowledged by the device (unless trying to write to an
invalid address).
7. If the host sends more than one data byte, they are written to consecutive memory addresses.
8. The device automatically increments the target memory address after writing each data byte.
9. After writing the last data byte, the host should send the STOP condition.
Note: the host should not try to write to addresses outside the range 0x20 to 0x39 because this is the limit of the
device internal memory address.
4.3.2 Reading Data From the Device
The sequence of events required to read data from the device is shown next.
1. The host initiates the transfer by sending the START condition
2. The host follows this by sending the slave address of the device together with the WRITE bit.
3. The device sends an ACK.
4. The host then sends the memory address within the device it wishes to read from.
5. The device sends an ACK if the address to be read from is less than 0x80 otherwise it sends a NACK).
6. The host must then send a STOP and a START condition followed by the slave address again but this time
accompanied by the READ bit.
Note: Alternatively, instead of step 6 a repeated START can be sent so the host does not need to
relinquish control of the bus.
7. The device returns an ACK, followed by a data byte.
8. The host must return either an ACK or NACK.
1. If the host returns an ACK, the device subsequently transmits the data byte from the next address. Each
time a data byte is transmitted, the device automatically increments the internal address. The device
continues to return data bytes until the host responds with a NACK.
2. If the host returns a NACK, it should then terminate the transfer by issuing the STOP condition.
9. The device resets the internal address to the location indicated by the memory address sent to it previously.
Therefore, there is no need to send the memory address again when reading from the same location.
Note: Reading the 16-bit reference and signal values is not an automatic operation; reading the first byte of a 16-
bit value does not lock the other byte. As a result glitches in the reported value may be seen as values
increase from 255 to 256, or decrease from 256 to 255.
4.4 SDA, SCL
The I
2
C bus transmits data and clock with SDA and SCL respectively. They are open-drain; that is I
2
C master and
slave devices can only drive these lines low or leave them open. The termination resistors pull the line up to Vdd if no
I
2
C device is pulling it down.
The termination resistors commonly range from 1 k to 10 k
and should be chosen so that the rise times on SDA
and SCL meet the I
2
C specifications (1 µs maximum).
Standalone mode: if I
2
C communications are not required, then standalone mode can be enabled by connecting the
MODE pin to Vdd. See Section 2.4 on page 8 for more information.
SLA+W
MemAddress
AAS
S
SLA+RA
A
P
Host to DeviceDevice Tx to Host
P
A
A
Data 1
Data 2
Data n
15
AT42QT1070 [DATASHEET]
9596C–AT42–05/2013
5. Setups
5.1 Introduction
The device calibrates and processes signals using a number of algorithms specifically designed to provide for high
survivability in the face of adverse environmental challenges. User-defined Setups are employed to alter these
algorithms to suit each application. These Setups are loaded into the device over the I
2
C serial interfaces. In
standalone mode these settings are fixed to predetermined values.
Table 5-1. Internal Register Address Allocation
Address Use Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W
0 Chip ID Major ID (= 2) Minor ID (= E)
R
1 Firmware Version Firmware version number
R
2 Detection status CALIBRATE OVERFLOW – – – – – TOUCH
R
3 Key status Reserved Key 6 Key 5 Key 4 Key 3 Key 2 Key 1
Key 0 R
4 – 5 Key signal 0 Key signal 0 (MSByte) – Key signal 0 (LSByte)
R
6 – 7 Key signal 1 Key signal 1 (MSByte) – Key signal 1 (LSByte)
R
8 – 9 Key signal 2 Key signal 2 (MSByte) – Key signal 2 (LSByte)
R
10 – 11 Key signal 3 Key signal 3 (MSByte) – Key signal 3 (LSByte)
R
12 – 13 Key signal 4 Key signal 4 (MSByte) – Key signal 4 (LSByte)
R
14 – 15 Key signal 5 Key signal 5 (MSByte) – Key signal 5 (LSByte)
R
16–17 Key signal 6 Key signal 6 (MSByte) – Key signal 6 (LSByte)
R
18 – 19 Reference data 0 Reference data 0 (MSByte) – Reference data 0 (LSByte)
R
20 – 21 Reference data 1 Reference data 1 (MSByte) – Reference data 1 (LSByte)
R
22 – 23 Reference data 2 Reference data 2 (MSByte) – Reference data 2 (LSByte)
R
24 – 25 Reference data 3 Reference data 3 (MSByte) – Reference data 3 (LSByte)
R
26 – 27 Reference data 4 Reference data 4 (MSByte) – Reference data 4 (LSByte)
R
28 – 29 Reference data 5 Reference data 5 (MSByte) – Reference data 5 (LSByte)
R
30–31 Reference data 6 Reference data 6 (MSByte) – Reference data 6 (LSByte)
R
32 NTHR key 0 Negative Threshold level for key 0
R/W
33 NTHR key 1 Negative Threshold level for key 1
R/W
34 NTHR key 2 Negative Threshold level for key 2
R/W
35 NTHR key 3 Negative Threshold level for key 3
R/W
36 NTHR key 4 Negative Threshold level for key 4
R/W
37 NTHR key 5 Negative Threshold level for key 5
R/W
38 NTHR key 6 Negative Threshold level for key 6
R/W
39 AVE/AKS key 0 Adjacent key suppression level for key 0
R/W
40 AVE/AKS key 1 Adjacent key suppression level for key 1
R/W
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P34

AT42QT1070-SSUR

Mfr. #:
Buy AT42QT1070-SSUR
Manufacturer:
Microchip Technology
Description:
Capacitive Touch Sensors QTouch 7 Channel Touch Sensor IC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet