LT3581
11
3581fb
For more information www.linear.com/LT3581
Sample Mode
Sample Mode is the mechanism used by the LT3581 to
aid in the detection of output shorts. It refers to a state of
the LT3581 where the master and slave power switches
(Q1 and Q2) are turned on for a minimum period of time
every clock cycle (or every few clock cycles in frequency
foldback) in order to “sample” the inductor current. If the
sampled current through Q1 exceeds the master switch cur
-
rent limit of 1.9A (min), the LT3581 triggers an overcurrent
fault
internally
(see Operation-Fault section for details).
Sample Mode is active when FB is out of regulation by
more than approximately 3.7% (45mV < FB < 1.17V).
Frequency Foldback
The frequency foldback circuit reduces the switching fre
-
quency when 350mV < FB < 900mV (typical). This feature
lowers the minimum duty cycle that the part can achieve,
thus allowing better control of the inductor current dur
-
ing start-up. When the FB voltage is pulled outside of this
range, the switching frequency returns to normal.
Note that the peak inductor current at start-up is a function
of many variables including load profile, output capacitance,
target V
OUT
, V
IN
, switching frequency, etc. Test each and
every application’s performance at start-up to ensure that
the peak inductor current does not exceed the minimum
fault current limit.
OPERATION – REGULATION
The following description of the LT3581’s operation as
-
sumes that the FB voltage is close enough to its regulation
target so that the part is not in sample mode. Use the
Block Diagram as a reference when stepping through the
following description of the LT3581 operating in regulation.
At the start of each oscillator cycle, the SR latch (SR1) is
set, which turns on the power switches Q1 and Q2. The
collector current through the master switch, Q1, is ~1.3
times the collector current through the slave switch, Q2,
when the collectors of the two switches are tied together.
OPERATION
Q1’s emitter current flows through a current sense resistor
(R
S
) generating a voltage proportional to the total switch
current. This voltage (amplified by A4) is added to a sta-
bilizing ramp and the resulting sum is fed into the positive
terminal of the P
WM comparator A3. When the voltage on
the positive input of A3 exceeds the voltage on the negative
input, the SR latch is reset, turning off the master and slave
power switches. The voltage on the negative input of A3
(V
C
pin) is set by A1 (or A2), which is simply an amplified
difference between the FB pin voltage and the reference
voltage (1.215V if the LT3581 is configured as a boost
converter, or 9mV if configured as an inverting converter).
In this manner, the error amplifier sets the correct peak
current level to maintain output regulation.
As long as the part is not in fault (see Operation – Fault
section) and the SS pin exceeds 1.8V, the LT3581 drives its
CLKOUT pin at the frequency set by the RT pin or the SYNC
pin. The CLKOUT pin can be used to synchronize other
compatible switching regulator ICs (including additional
LT3581s) with the LT3581. Additionally, CLKOUT’s duty
cycle varies linearly with the part’s junction temperature,
and may be used as a temperature monitor.
OPERATION – FAULT
The LT3581’s FAULT pin is an active low, bidirectional pin
that is pulled low to indicate a fault. Each of the following
events can trigger a fault in the LT3581:
A. FAULT1 events:
1. SW Overcurrent:
a. I
SW1
> 1.9A (minimum)
b. (I
SW1
+ I
SW2
) > 3.3A (minimum)
2. V
IN
Voltage > 22V (minimum)
3. SW1 Voltage and/or SW2 Voltage > 42V
(minimum)
4. Die Temperature > 165°C
B. FAULT2 events:
1. Pulling the FAULT pin low externally
