LT3581
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For more information www.linear.com/LT3581
APPENDIX
SETTING THE OUTPUT VOLTAGE
The output voltage is set by connecting a resistor (R
FB
)
from V
OUT
to the FB pin. R
FB
is determined by using the
following equation:
R
FB
=
|V
OUT
V
FB
|
83.3µA
where V
FB
is 1.215V (typical) for non-inverting topologies
(i.e. boost and SEPIC regulators) and 5mV (typical) for
inverting topologies.
POWER SWITCH DUTY CYCLE
In order to maintain loop stability and deliver adequate
current to the load, the power NPNs (Q1 and Q2 in the
Block Diagram) cannot remain “on” for 100% of each clock
cycle. The maximum allowable duty cycle is given by:
DC
MAX
=
T
P
MinOffTime
( )
T
P
100%
where T
P
is the clock period and MinOffTime (found in the
Electrical Characteristics) is typically 60ns.
Conversely, the power NPNs (Q1 and Q2 in the Block Dia
-
gram) cannot remain “off” for 100% of each clock cycle,
and will turn on for a minimum on time (MinOnTime) when
in regulation. This MinOnTime governs the minimum al
-
lowable duty cycle given by:
DC
MIN
=
MinOnTime
( )
T
P
100%
Where T
P
is the clock period and MinOnTime (found in
the Electrical Characteristics) is typically 100ns.
The application should be designed such that the operating
duty cycle is between DC
MIN
and DC
MAX
.
Duty cycle equations for several common topologies are given
below where V
D
is the diode forward voltage drop and V
CESAT
is the collector to emitter saturation voltage of the switch.
V
CESAT
, with SW1 and SW2 tied together, is typically 250mV
when the combined switch current (I
SW1
+ I
SW2
) is 2.75A.
For the boost topology (see Figure 5):
DC
BOOST
V
OUT
V
IN
+V
D
V
OUT
+V
D
V
CESAT
For the SEPIC or Dual Inductor Inverting topology (see
Figures 6 and 7):
DC
SEPIC _&_INVERT
V
D
+| V
OUT
|
V
IN
+| V
OUT
| + V
D
V
CESAT
For the Single Inductor Inverting topology (see Figure 13):
DC
SI_INVERT
=
|V
OUT
|V
IN
+ V
CESAT
+ 3V
D
|V
OUT
| + 3V
D
The LT3581 can be used in configurations where the duty
cycle is higher than DC
MAX
, but it must be operated in
the discontinuous conduction mode so that the effective
duty cycle is reduced.
INDUCTOR SELECTION
General Guidelines: The high frequency operation of the
LT3581 allows for the use of small surface mount inductors.
For high efficiency, choose inductors with high frequency
core material, such as ferrite, to reduce core losses. Also
to improve efficiency, choose inductors with more volume
for a given inductance. The inductor should have low
DCR (copper-wire resistance) to reduce I
2
R losses, and
must be able to handle the peak inductor current without
saturating. Note that in some applications, the current
handling requirements of the inductor can be lower, such
as in the SEPIC topology where each inductor only carries
one half of the total switch current. Molded chokes or chip
inductors usually do not have enough core area to support
peak inductor currents in the 2A to 6A range. To minimize
radiated noise, use a toroidal or shielded inductor. See
Table 5 for a list of inductor manufacturers.
Table 5. Inductor Manufacturers
Sumida CDR6D28MN and CDR7D28MN
Series
www.sumida.com
Coilcraft MSD7342 Series www.coilcraft.com
Vishay IHLP-1616BZ-01, IHLP-2020BZ-01
and IHLP-2525CZ-01 Series
www.vishay.com
Taiyo Yuden NR Series www.t-yuden.com
Wurth WE-PD Series www.we-online.com
TDK VLF, SLF and RLF Series www.tdk.com
LT3581
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For more information www.linear.com/LT3581
Minimum Inductance
Although there can be a tradeoff with efficiency, it is often
desirable to minimize board space by choosing smaller
inductors. When choosing an inductor, there are three
conditions that limit the minimum inductance: (1) provid
-
ing adequate load current, (2) avoidance of subharmonic
oscillations and (3) supplying a minimum ripple current
to avoid false tripping of the current comparator
.
Adequate Load Current
Small value inductors result in increased ripple currents and
thus, due to the limited peak switch current, decrease the
average current that can be provided to the load. In order
to provide adequate load current, L should be at least:
L
BOOST
>
DC V
IN
V
CESAT
( )
2f
OSC
I
PK
|V
OUT
|I
OUT
V
IN
η
or
L
DUAL
>
DC V
IN
V
CESAT
( )
2f
OSC
I
PK
|V
OUT
|I
OUT
V
IN
η
I
OUT
Boost
Topology
SEPIC
or
Inverting
Topologies
where:
L
BOOST
= L
1
for Boost Topologies (see Figure 5)
L
DUAL
= L
1
= L
2
for Coupled Dual Inductor
Topologies (see Figures 6 and 7)
L
DUAL
= L
1
|| L
2
for Uncoupled Dual Inductor
Topologies (see Figures 6 and 7)
DC = Switch Duty Cycle (see Power Switch Duty
Cycle section in Appendix)
I
PK
= Maximum Peak Switch Current; should not
exceed 3.3A for a combined SW1 + SW2
current, or 1.9A of SW1 current if SW1 is
being used by itself.
η = Power Conversion Efficiency (typically 88%
for Boost and 75% for Dual Inductor
Topologies at High Currents)
f
OSC
= Switching Frequency
I
OUT
= Maximum Output Current
APPENDIX
Negative values of L
BOOST
or L
DUAL
indicate that the out-
put load current, I
OUT
, exceeds the switch current limit
capability of the LT3581.
Avoiding Sub-Harmonic Oscillations
The LT3581’s internal slope compensation circuit will
prevent sub-harmonic oscillations that can occur when
the duty cycle is greater than 50%, provided that the
inductance exceeds a certain minimum value. In applica
-
tions that operate with duty cycles greater than 50%, the
inductance must be at least:
L
MIN
=
V
IN
V
CESAT
( )
2 DC1
( )
2.2Af
OSC
1DC
( )
where:
L
MIN
= L
1
for Boost Topologies (see Figure 5)
L
MIN
= L
1
= L
2
for Coupled Dual Inductor
Topologies (see Figures 6 and 7)
L
MIN
= L
1
|| L
2
for Uncoupled Dual Inductor
Topologies (see Figures 6 and 7)
Maximum Inductance
Excessive inductance can reduce ripple current to levels
that are difficult for the current comparator (A4 in the Block
Diagram) to cleanly discriminate, causing duty cycle jitter
and/or poor regulation. The maximum inductance can be
calculated by:
L
MAX
=
V
IN
V
CESAT
350mA
DC
f
OSC
where:
L
MAX
= L
1
for Boost Topologies (see Figure 5)
L
MAX
= L
1
= L
2
for Coupled Dual Inductor
Topologies (see Figures 6 and 7)
L
MAX
= L
1
|| L
2
for Uncoupled Dual Inductor
Topologies (see Figures 6 and 7)
LT3581
24
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For more information www.linear.com/LT3581
APPENDIX
Inductor Current Rating
Inductors must have a rating greater than their peak
operating current, or else they could saturate and hence
contribute to losses in efficiency. The maximum inductor
current (considering start-up and steady-state conditions)
is given by:
I
L _PEAK
=I
LIM
+
V
IN
T
MIN _ PROP
L
where:
I
L_PEAK
= Peak Inductor Current in L
1
for a Boost
Topology, or the Peak of the sum of the
Inductor Currents in L1 and L2 for Dual
Inductor Topologies.
I
LIM
** = 3.3A with SW1 and SW2 Tied Together,
or 1.9A with just SW1 (This assumes
usage of an inductor whose core
material soft-saturates such as
powdered iron core).
T
MIN_PROP
= 100ns (Propagation Delay through the
Current Feedback Loop).
**If using an inductor whose core material saturates
hard (e.g., ferrite), then pick I
LIM
to be 5.4A with SW1
and SW2 tied together, or 3A when just SW1 is used.
Note that these equations offer conservative results for
the required inductor current ratings. The current ratings
could be lower for applications with light loads, if the SS
capacitor is sized appropriately to limit inductor currents
at start-up.
DIODE SELECTION
Schottky diodes, with their low forward voltage drops and
fast switching speeds, are recommended for use with the
LT3581. Choose a Schottky diode with low parasitic capaci
-
tance to reduce reverse current spikes through the power
switch of the L
T3581. The Central Semiconductor Corp.
CMMSH2-40 diode is a very good choice with a 40V reverse
voltage rating and an average forward current of 2A.
OUTPUT CAPACITOR SELECTION
Low ESR (equivalent series resistance) capacitors should
be used at the output to minimize the output ripple voltage.
Multilayer ceramic capacitors are an excellent choice, as
they have extremely low ESR and are available in very
small packages. X5R or X7R dielectrics are preferred, as
these materials retain their capacitance over wide voltage
and temperature ranges. A 10μF to 22μF output capacitor
is sufficient for most applications, but systems with very
low output currents may need only 2.2μF to 10μF. Always
use a capacitor with a sufficient voltage rating. Many
ceramic capacitors, particularly 0805 or 0603 case sizes,
have greatly reduced capacitance at the desired output
voltage. Tantalum Polymer or OS-CON capacitors can be
used, but it is likely that these capacitors will occupy more
board area than a ceramic, and will have higher ESR with
greater output ripple.
INPUT CAPACITOR SELECTION
Ceramic capacitors make a good choice for the input
decoupling capacitor, and should be placed such that it is
in close proximity to the V
IN
of the chip as well as to the
inductor connected to the input of the power path. If it is
not possible to optimally place a single input capacitor,
then use two separate capacitors—use one at the V
IN
of
the chip (see equation for C
VIN
in Tables 1, 2 and 3) and
one at the input to the power path (see equation for C
PWR
in Tables 1, 2 and 3) A 4.7μF to 20μF input capacitor is
sufficient for most applications.
Table 6 shows a list of several ceramic capacitor man-
ufacturers. Consult the manufacturers for detailed infor-
mation on their entire selection of ceramic parts.
Table 6: Ceramic Capacitor Manufacturers
AVX www.avxcorp.com
Murata www.murata.com
Taiyo Yuden www.t-yuden.com
PMOS SELECTION
An external PMOS, controlled by the LT3581’s GATE pin,
can be used to facilitate input or output disconnect. The
GATE pin turns on the PMOS gradually during start-up
(see Soft-Start of External PMOS in the Operation section),
and turns the PMOS off when the LT3581 is in shutdown
or in fault.

LT3581EMSE#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 3A Boost/Inverting DC/DC Converter with Fault Protection
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