PCA9685 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 16 April 2015 16 of 52
NXP Semiconductors
PCA9685
16-channel, 12-bit PWM Fm+ I
2
C-bus LED controller
7.3.2 Mode register 2, MODE2
[1] See Section 7.7 “Using the PCA9685 with and without external drivers” for more details. Normal LEDs can be driven directly in either
mode. Some newer LEDs include integrated Zener diodes to limit voltage transients, reduce EMI, protect the LEDs and these must be
driven only in the open-drain mode to prevent overheating the IC. Power on reset default state of LEDn output pins is LOW.
[2] Change of the outputs at the STOP command allows synchronizing outputs of more than one PCA9685. Applicable to registers from
06h (LED0_ON_L) to 45h (LED15_OFF_H) only. 1 or more registers can be written, in any order, before STOP.
[3] Update on ACK requires all 4 PWM channel registers to be loaded before outputs will change on the last ACK.
[4] See Section 7.4 “
Active LOW output enable input” for more details.
7.3.3 LED output and PWM control
The turn-on time of each LED driver output and the duty cycle of PWM can be controlled
independently using the LEDn_ON and LEDn_OFF registers.
There will be two 12-bit registers per LED output. These registers will be programmed by
the user. Both registers will hold a value from 0 to 4095. One 12-bit register will hold a
value for the ON time and the other 12-bit register will hold the value for the OFF time. The
ON and OFF times are compared with the value of a 12-bit counter that will be running
continuously from 0000h to 0FFFh (0 to 4095 decimal).
Update on ACK requires all 4 PWM channel registers to be loaded before outputs will
change on the last ACK.
The ON time, which is programmable, will be the time the LED output will be asserted and
the OFF time, which is also programmable, will be the time when the LED output will be
negated. In this way, the phase shift becomes completely programmable. The resolution
for the phase shift is
1
⁄
4096
of the target frequency. Table 7 lists these registers.
The following two examples illustrate how to calculate values to be loaded into these
registers.
Table 6. MODE2 - Mode register 2 (address 01h) bit description
Legend: * default value.
Bit Symbol Access Value Description
7 to 5 - read only 000* reserved
4INVRT
[1]
R/W 0* Output logic state not inverted. Value to use when external driver used.
Applicable when OE
=0.
1 Output logic state inverted. Value to use when no external driver used.
Applicable when OE
=0.
3 OCH R/W 0* Outputs change on STOP command
[2]
.
1 Outputs change on ACK
[3]
.
2OUTDRV
[1]
R/W 0 The 16 LEDn outputs are configured with an open-drain structure.
1* The 16 LEDn outputs are configured with a totem pole structure.
1to0 OUTNE[1:0]
[4]
R/W 00* When OE = 1 (output drivers not enabled), LEDn = 0.
01 When OE
= 1 (output drivers not enabled):
LEDn = 1 when OUTDRV = 1
LEDn = high-impedance when OUTDRV = 0 (same as OUTNE[1:0] = 10)
1X When OE = 1 (output drivers not enabled), LEDn = high-impedance.
