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PCA9685BS,118

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P52
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PCA9685 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 16 April 2015 40 of 52
NXP Semiconductors
PCA9685
16-channel, 12-bit PWM Fm+ I
2
C-bus LED controller
13. Dynamic characteristics
Table 15. Dynamic characteristics
Symbol Parameter Conditions Standard-mode
I
2
C-bus
Fast-mode I
2
C-bus Fast-mode Plus
I
2
C-bus
Unit
Min Max Min Max Min Max
f
SCL
SCL clock frequency
[1]
0 100 0 400 0 1000 kHz
f
EXTCLK
frequency on pin EXTCLK DC 50 DC 50 DC 50 MHz
t
BUF
bus free time between a STOP
and START condition
4.7 - 1.3 - 0.5 - s
t
HD;STA
hold time (repeated) START
condition
4.0 - 0.6 - 0.26 - s
t
SU;STA
set-up time for a repeated
START condition
4.7 - 0.6 - 0.26 - s
t
SU;STO
set-up time for STOP condition 4.0 - 0.6 - 0.26 - s
t
HD;DAT
data hold time 0 - 0 - 0 - ns
t
VD;ACK
data valid acknowledge time
[2]
0.3 3.45 0.1 0.9 0.05 0.45 s
t
VD;DAT
data valid time
[3]
0.3 3.45 0.1 0.9 0.05 0.45 s
t
SU;DAT
data set-up time 250 - 100 - 50 - ns
t
LOW
LOW period of the SCL clock 4.7 - 1.3 - 0.5 - s
t
HIGH
HIGH period of the SCL clock 4.0 - 0.6 - 0.26 - s
t
f
fall time of both SDA and SCL
signals
[4][5]
- 300 20 + 0.1C
b
[6]
300 - 120 ns
t
r
rise time of both SDA and SCL
signals
- 1000 20 + 0.1C
b
[6]
300 - 120 ns
t
SP
pulse width of spikes that must
be suppressed by the input filter
[7]
-50 - 50-50ns
t
PLZ
LOW to OFF-state propagation
delay
OE to LEDn;
OUTNE[1:0] = 10 or 11
in MODE2 register
-40 - 40-40ns
t
PZL
OFF-state to LOW propagation
delay
OE to LEDn;
OUTNE[1:0] = 10 or 11
in MODE2 register
-60 - 60-60ns
t
PHZ
HIGH to OFF-state propagation
delay
OE to LEDn;
OUTNE[1:0] = 10 or 11
in MODE2 register
-60 - 60-60ns
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
PCA9685 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 16 April 2015 41 of 52
NXP Semiconductors
PCA9685
16-channel, 12-bit PWM Fm+ I
2
C-bus LED controller
[1] Minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if either SDA or SCL is held LOW for a minimum of 25 ms.
Disable bus time-out feature for DC operation.
[2] t
VD;ACK
= time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
[3] t
VD;DAT
= minimum time for SDA data out to be valid following SCL LOW.
[4] A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the V
IL
of the SCL signal) in order to bridge the undefined region of
SCL’s falling edge.
[5] The maximum t
f
for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time (t
f
) for the SDA output stage is specified at 250 ns. This allows series
protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified t
f
.
[6] C
b
= total capacitance of one bus line in pF.
[7] Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.
t
PZH
OFF-state to HIGH propagation
delay
OE to LEDn;
OUTNE[1:0] = 10 or 11
in MODE2 register
-40 - 40-40ns
t
PLH
LOW to HIGH propagation delay OE to LEDn;
OUTNE[1:0] = 01
in MODE2 register
-40 - 40-40ns
t
PHL
HIGH to LOW propagation delay OE to LEDn;
OUTNE[1:0] = 00
in MODE2 register
-60 - 60-60ns
Table 15. Dynamic characteristics
…continued
Symbol Parameter Conditions Standard-mode
I
2
C-bus
Fast-mode I
2
C-bus Fast-mode Plus
I
2
C-bus
Unit
Min Max Min Max Min Max
PCA9685 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 16 April 2015 42 of 52
NXP Semiconductors
PCA9685
16-channel, 12-bit PWM Fm+ I
2
C-bus LED controller
Fig 31. Definition of timing
t
SP
t
BUF
t
HD;STA
PP S
t
LOW
t
r
t
HD;DAT
t
f
t
HIGH
t
SU;DAT
t
SU;STA
Sr
t
HD;STA
t
SU;STO
DA
CL
002aaa9
0.7 × V
0.3 × V
0.7 × V
0.3 × V
Rise and fall times refer to V
IL
and V
IH
.
Fig 32. I
2
C-bus timing diagram
Fig 33. t
PLZ
, t
PZL
and t
PHZ
, t
PZH
times
SCL
SDA
t
HD;STA
t
SU;DAT
t
HD;DAT
t
f
t
BUF
t
SU;STA
t
LOW
t
HIGH
t
VD;ACK
002aab285
t
SU;STO
protocol
START
condition
(S)
bit 7
MSB
(A7)
bit 6
(A6)
bit 1
(D1)
bit 0
(D0)
1
/ f
SCL
t
r
t
VD;DAT
acknowledge
(A)
STOP
condition
(P)
0.3 × V
DD
0.7 × V
DD
0.3 × V
DD
0.7 × V
DD
002aad810
t
PLZ
t
PHZ
outputs
disabled
outputs
enabled
outputs
enabled
LEDn output
LOW-to-OFF
OFF-to-LOW
LEDn output
HIGH-to-OFF
OFF-to-HIGH
OE input
V
I
V
OL
V
OH
V
DD
V
M
V
M
V
X
V
Y
V
M
V
SS
t
PZL
t
PZH
V
M
V
SS
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P52

PCA9685BS,118

Mfr. #:
Buy PCA9685BS,118
Manufacturer:
NXP Semiconductors
Description:
LED Display Drivers 16-CH 12-BIT PWM FM+ I2C-BUS LED CTRL
Lifecycle:
New from this manufacturer.
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