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PCA9685BS,118

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P52
PCA9685 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 16 April 2015 25 of 52
NXP Semiconductors
PCA9685
16-channel, 12-bit PWM Fm+ I
2
C-bus LED controller
7.3.4 ALL_LED_ON and ALL_LED_OFF control
The ALL_LED_ON and ALL_LED_OFF registers allow just four I
2
C-bus write sequences
to fill all the ON and OFF registers with the same patterns.
The LEDn_ON and LEDn_OFF counts can vary from 0 to 4095. The LEDn_ON and
LEDn_OFF count registers should never be programmed with the same values.
Because the loading of the LEDn_ON and LEDn_OFF registers is via the I
2
C-bus, and
asynchronous to the internal oscillator, we want to ensure that we do not see any visual
artifacts of changing the ON and OFF values. This is achieved by updating the changes at
the end of the LOW cycle.
7.3.5 PWM frequency PRE_SCALE
The hardware forces a minimum value that can be loaded into the PRE_SCALE register
at ‘3’. The PRE_SCALE register defines the frequency at which the outputs modulate. The
prescale value is determined with the formula shown in Equation 1
:
(1)
where the update rate is the output modulation frequency required. For example, for an
output default frequency of 200 Hz with an oscillator clock frequency of 25 MHz:
(2)
The maximum PWM frequency is 1526 Hz if the PRE_SCALE register is set "0x03h".
The minimum PWM frequency is 24 Hz if the PRE_SCALE register is set "0xFFh".
The PRE_SCALE register can only be set when the SLEEP bit of MODE1 register is set to
logic 1.
Table 8. ALL_LED_ON and ALL_LED_OFF control registers (address FAh to FEh) bit description
Legend: * default value.
Address Register Bit Symbol Access Value Description
FAh ALL_LED_ON_L 7:0 ALL_LED_ON_L[7:0] W only
0000 0000*
LEDn_ON count for ALL_LED, 8 MSBs
FBh ALL_LED_ON_H 7:5 reserved R
000*
non-writable
4 ALL_LED_ON_H[4] W only
1*
ALL_LED full ON
3:0 ALL_LED_ON_H[3:0] W only
0000*
LEDn_ON count for ALL_LED, 4 MSBs
FCh ALL_LED_OFF_L 7:0 ALL_LED_OFF_L[7:0] W only
0000 0000*
LEDn_OFF count for ALL_LED,
8 MSBs
FDh ALL_LED_OFF_H 7:5 reserved R
000*
non-writable
4 ALL_LED_OFF_H[4] W only
1*
ALL_LED full OFF
3:0 ALL_LED_OFF_H[3:0] W only
0000*
LEDn_OFF count for ALL_LED,
4 MSBs
FEh PRE_SCALE 7:0 PRE_SCALE[7:0] R/W
0001 1110*
prescaler to program the PWM output
frequency (default is 200 Hz)
prescale value round
osc_clock
4096 update_rate
--------------------------------------------------


1–=
prescale value round
25 MHz
4096 200
---------------------------


1– 30 0x1Eh==
PCA9685 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 16 April 2015 26 of 52
NXP Semiconductors
PCA9685
16-channel, 12-bit PWM Fm+ I
2
C-bus LED controller
7.3.6 SUBADR1 to SUBADR3, I
2
C-bus subaddress 1 to 3
Subaddresses are programmable through the I
2
C-bus. Default power-up values are E2h,
E4h, E8h, and the device(s) will not acknowledge these addresses right after power-up
(the corresponding SUBx bit in MODE1 register is equal to 0).
Once subaddresses have been programmed to their right values, SUBx bits need to be
set to logic 1 in order to have the device acknowledging these addresses (MODE1
register).
Only the 7 MSBs representing the I
2
C-bus subaddress are valid. The LSB in SUBADRx
register is a read-only bit (0).
When SUBx is set to logic 1, the corresponding I
2
C-bus subaddress can be used during
either an I
2
C-bus read or write sequence.
7.3.7 ALLCALLADR, LED All Call I
2
C-bus address
The LED All Call I
2
C-bus address allows all the PCA9685s in the bus to be programmed
at the same time (ALLCALL bit in register MODE1 must be equal to 1 (power-up default
state)). This address is programmable through the I
2
C-bus and can be used during either
an I
2
C-bus read or write sequence. The register address can also be programmed as a
Sub Call.
Only the 7 MSBs representing the All Call I
2
C-bus address are valid. The LSB in
ALLCALLADR register is a read-only bit (0).
If ALLCALL bit = 0, the device does not acknowledge the address programmed in register
ALLCALLADR.
Table 9. SUBADR1 to SUBADR3 - I
2
C-bus subaddress registers 0 to 3 (address 02h to
04h) bit description
Legend: * default value.
Address Register Bit Symbol Access Value Description
02h SUBADR1 7:1 A1[7:1] R/W
1110 001*
I
2
C-bus subaddress 1
0 A1[0] R only
0*
reserved
03h SUBADR2 7:1 A2[7:1] R/W
1110 010*
I
2
C-bus subaddress 2
0 A2[0] R only
0*
reserved
04h SUBADR3 7:1 A3[7:1] R/W
1110 100*
I
2
C-bus subaddress 3
0 A3[0] R only
0*
reserved
Table 10. ALLCALLADR - LED All Call I
2
C-bus address register (address 05h) bit
description
Legend: * default value.
Address Register Bit Symbol Access Value Description
05h ALLCALLADR 7:1 AC[7:1] R/W
1110 000*
ALLCALL I
2
C-bus
address register
0 AC[0] R only
0*
reserved
PCA9685 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 16 April 2015 27 of 52
NXP Semiconductors
PCA9685
16-channel, 12-bit PWM Fm+ I
2
C-bus LED controller
7.4 Active LOW output enable input
The active LOW output enable (OE) pin, allows to enable or disable all the LED outputs at
the same time.
• When a LOW level is applied to OE pin, all the LED outputs are enabled and follow
the output state defined in the LEDn_ON and LEDn_OFF registers with the polarity
defined by INVRT bit (MODE2 register).
• When a HIGH level is applied to OE pin, all the LED outputs are programmed to the
value that is defined by OUTNE[1:0] in the MODE2 register.
The OE pin can be used as a synchronization signal to switch on/off several PCA9685
devices at the same time. This requires an external clock reference that provides blinking
period and the duty cycle.
The OE
pin can also be used as an external dimming control signal. The frequency of the
external clock must be high enough not to be seen by the human eye, and the duty cycle
value determines the brightness of the LEDs.
7.5 Power-on reset
When power is applied to V
DD
, an internal power-on reset holds the PCA9685 in a reset
condition until V
DD
has reached V
POR
. At this point, the reset condition is released and the
PCA9685 registers and I
2
C-bus state machine are initialized to their default states.
Thereafter, V
DD
must be lowered below 0.2 V to reset the device.
Table 11. LED outputs when OE =1
OUTNE1 OUTNE0 LED outputs
000
0 1 1 if OUTDRV = 1, high-impedance if OUTDRV = 0
1 0 high-impedance
1 1 high-impedance
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P52

PCA9685BS,118

Mfr. #:
Buy PCA9685BS,118
Manufacturer:
NXP Semiconductors
Description:
LED Display Drivers 16-CH 12-BIT PWM FM+ I2C-BUS LED CTRL
Lifecycle:
New from this manufacturer.
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