LTM4608
7
4608fd
PLLLPF (E3): Phase-Locked Loop Lowpass Filter. An in-
ternal lowpass filter is tied to this pin. In spread spectrum
mode, placing a capacitor here to SGND controls the slew
rate from one frequency to the next. Alternatively, floating
this pin allows normal running frequency at 1.5MHz, tying
this pin to SV
IN
forces the part to run at 1.33 times its
normal frequency (2MHz), tying it to ground forces the
frequency to run at 0.67 times its normal frequency (1MHz).
PHMODE (B4): Phase Selector Input. This pin determines
the phase relationship between the internal oscillator and
CLKOUT. Tie it high for 2-phase operation, tie it low for
3-phase operation, and float or tie it to V
IN
/2 for 4-phase
operation.
MGN (B8): Margining Pin. Increases or decreases the
output voltage by the amount specified by the BSEL pin.
To disable margining, tie the MGN pin to a voltage divider
with 50k resistors from V
IN
to ground. See the Applications
Information section and Figure 20.
BSEL (B7): Margining Bit Select Pin. Tying BSEL low se-
lects ±5%, tying it high selects ±10%. Floating it or tying
it to V
IN
/2 selects ±15%.
TRACK (E5): Output Voltage Tracking Pin. Voltage track-
ing is enabled when the TRACK voltage is below 0.57V.
If tracking is not desired, then connect the TRACK pin to
SV
IN
. If TRACK is not tied to SV
IN
, then the TRACK pin’s
voltage needs to be below 0.18V before the chip shuts
down even though RUN is already low. Do not float this
pin. A resistor divider and capacitor can be applied to the
TRACK pin to increase the soft-start time of the regulator.
See the Applications Information section. Can tie together
for parallel operation and tracking. Load current needs to
be present during track down.
pin FuncTions
V
IN
(C1, C8, C9, D1, D3-D5, D7-D9 and E8): Power Input
Pins. Apply input voltage between these pins and GND
pins. Recommend placing input decoupling capacitance
directly between V
IN
pins and GND pins.
V
OUT
(C10-C11, D10-D11, E9-E11, F9-F11, G9-G11):
Power Output Pins. Apply output load between these pins
and GND pins. Recommend placing output decoupling
capacitance directly between these pins and GND pins.
See Table 1.
GND (A1-A11, B1, B9-B11, F3, F7-F8, G1-G8): Power
Ground Pins for Both Input and Output Returns.
SV
IN
(F4): Signal Input Voltage. This pin is internally con-
nected to V
IN
through a lowpass filter.
SGND (E1): Signal Ground Pin. Return ground path for all
analog and low power circuitry. Tie a single connection to
GND in the application.
MODE (B5): Mode Select Input. Tying this pin high enables
Burst Mode
®
operation. Tying this pin low enables forced
continuous operation. Floating this pin or tying it to V
IN
/2
enables pulse-skipping operation.
CLKIN (B3): External Synchronization Input to Phase
Detector. This pin is internally terminated to SGND with a
50k resistor. The phase-locked loop will force the internal
top power PMOS turn on to be synchronized with the
rising edge of the CLKIN signal. Connect this pin to SV
IN
to enable spread spectrum modulation. During external
synchronization, make sure the PLLLPF pin is not tied to
V
IN
or GND.
