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ISL5314IN

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
13
FN4901.3
January 19, 2010
Timing Diagrams
FIGURE 3. PARALLEL-LOAD METHOD 1, UPDATE ACTIVE AFTER LOADING REGISTERS (RESET = HIGH)
FIGURE 4. PARALLEL-LOAD METHOD 2, UPDATE
ACTIVE WHILE LOADING REGISTERS (RESET = HIGH)
WRITE
t
DS
t
DH
DATA
W
1
W
2
CLK (f
CLK
)
OLD FREQ
NEW FREQ
ANALOG OUT
t
UL
= 14 CLK RISING EDGES
UPDATE
t
US
t
UD
t
AS
t
AH
ADDR
A
1
A
2
WE
t
WS
t
WH
ADDR
A
0
W
0
A
N
W
N
DON’T CARE
DON’T CARE
DON’T CARE
DON’T CARE
1 WRITE CYCLE FOR EVERY REGISTER
PREVIOUS FREQ
ENTIRE NEW FREQ
ANALOG OUT
t
UL
= 11 CLK RISING EDGES
UPDATE
WRITE
t
DS
t
DH
DATA
CLK (f
CLK
)
1 WRITE CYCLE FOR EVERY REGISTER
t
AS
t
AH
ADDR
PARTIAL UPDATES
WE
t
WS
t
WH
DON’T CARE
DON’T CARE
DON’T CARE
DON’T CARE
A
1
A
2
A
0
A
N
W
1
W
2
W
0
W
N
ISL5314
14
FN4901.3
January 19, 2010
FIGURE 5. RESET TIMING AND LATENCY
FIGURE 6. ENOFR (ENABLE OFFSET FREQUENCY REGISTER) TIMING AND LATENCY (RESET
= HIGH)
Timing Diagrams (Continued)
CLK (f
CLK
)
PREVIOUS REGISTER VALUES
RESET REGISTER VALUES
ANALOG OUT
t
RL
= 11 CLK RISING EDGES
RESET
ONE CLK RISING EDGE
t
RS
REQUIRED WHILE RESET LOW
CLK (f
CLK
)
CENTER FREQUENCY ONLY CENTER + OFFSET
ANALOG OUT
t
EL
= 14 CLK RISING EDGES
t
EH
ENOFR
CENTER ONLY
CENTER
+ OFFSET
t
ES
ISL5314
15
FN4901.3
January 19, 2010
FIGURE 7. SERIAL PROGRAMMING, SYNC EARLY MODE (REPRESENTS MINIMUM SCLKS REQUIRED. SCLK CAN FREE RUN.)
CONTROL REGISTER 12 IS SET TO 0001 00XX.
FIGURE 8. SERIAL PROGRAMMING, SYNC LATE BURST MODE (REPRESENTS MINIMUM SCLKS REQUIRED; SCLK CAN FREE RUN);
CONTROL REGISTER 12 IS SET TO 0000 00XX.
Timing Diagrams (Continued)
SSYNC
SDATA
CLK (f
CLK
)
ANALOG OUT
t
= 12 f
CLK
RISING EDGES
OLD FREQ IN THE
NEW FREQ LOADED
SERIAL FREQ
REGISTER
SERIAL DATA (8 BITS SHOWN; MAX IS 40)
SCLK
SCLK EDGES = SERIAL BITS + 3
SERIAL REGISTER
IN THE SERIAL REGISTER
DON’T CARE (CAN FREE RUN)
DON’T CARE (ASSUMED CONTINUOUSLY RUNNING)
DON’T CARE
RESET
OLD FREQ
NEW FREQ
DON’T CARE
t
SDH
t
SDS
t
SSH
t
SSS
t
SCW
t
SSW
t
SDW
SSYNC
SDATA
CLK (f
CLK
)
ANALOG OUT
t
= 12 f
CLK
RISING EDGES
OLD FREQ IN THE
NEW FREQ LOADED
SERIAL FREQ
REGISTER
SERIAL DATA (8 BITS SHOWN; MAX IS 40)
SCLK
SCLK EDGES = SERIAL BITS + 3
SERIAL REGISTER
IN THE SERIAL REGISTER
DON’T CARE (CAN FREE RUN)
DON’T CARE (ASSUMED CONTINUOUSLY RUNNING)
DON’T CARE
RESET
OLD FREQ
NEW FREQ
DON’T CARE
ISL5314
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

ISL5314IN

Mfr. #:
Buy ISL5314IN
Manufacturer:
Renesas / Intersil
Description:
Digital Signal Processors & Controllers - DSP, DSC DIRECT DIGTL SYNTHESIZER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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