4
FN4901.3
January 19, 2010
Functional Description
The ISL5314 is an NCO with an integrated 14-bit DAC
designed to run in excess of 125MSPS. The NCO is a 16-bit
output design, which is rounded to fourteen bits for input to the
DAC. The frequency control is the sum of a 48-bit center
frequency word, a 48-bit offset frequency word, and a 40-bit
serially loaded tuning word. The three components are added
modulo 48 bits with the alignment shown in Table 1. Each of the
three terms can be zeroed independently (via the
microprocessor interface for the center and serial frequency
registers and via the ENOFR pin for the offset frequency term).
Frequency Generation
The output frequency of the part is determined by the
summation of three registers as shown in Equation 1:
where CF is the center frequency register, OF is the offset
frequency register, SF is the serial frequency register and
f
CLK
is the DDS clock rate.
With a 125MSPS clock rate, the center frequency can be
programmed to Equation 2:
The addition of the frequency control words can be interpreted
as two’s complement if convenient. For example, if the center
frequency is set to 4000...00h and the offset frequency set to
C000..00h, the programmed center frequency would be f
CLK
/4
and the programmed offset frequency -f
CLK
/4. The sum would
be 10000..00h, but because only the lower 48 bits are retained,
the effective frequency would be 0. In reality, frequencies above
8000...00h alias below f
CLK
/2 (the output of the part is real), so
the MSB is only provided as a convenience for two’s
complement calculations.
The frequency control of the NCO is the change in phase per
clock period or dφ/dt. This is integrated by the phase
accumulator to obtain frequency. The most significant 24 bits
of phase are then mapped to 16 bits of amplitude in a sine
look-up table function. The range of dφ/dt is 0–1 with 1
equaling 360° or (2 x pi) per clock period. The phase
accumulator output is also 0–1 with 1 equaling 360°. The
operations are modulo 48 bits because the MSB (Bit 47)
aligns with the most significant address bit of the sine ROM
and the ROM contains one cycle of a sinusoid. The MSB is
weighted at 180°. Full scale is 360° minus one LSB and the
phase then rolls over to 0° for the next cycle of the sinusoid.
The DDS can be clocked with either a sinusoidal or a square
wave. Refer to the digital inputs V
IH
and V
IL
values in the
electrical specifications table.
Parallel Interface
The processor interface is an 8-bit parallel write only
interface. The interface consists of eight data bits (C7:C0),
four address pins (A3:A0), a write strobe (WR), and a write
enable (WE
). The interface is a master/slave type. The
processor interface loads a set of master registers. The
contents of the master set of registers is then transferred to a
slave set of registers by asserting a pin (UPDATE
). This
allows all of the bits of the frequency control to be updated
simultaneously.
The rate which the user writes (WR) to these registers does not
have to be the same rate as the DDS clock rate (the rate of the
NCO and DAC; pin CLK). It is expected that most applications
will have a slower register write rate than the DDS clock rate. It
takes one WR cycle at the write rate for each register that is
written and another eleven CLK cycles at the DDS rate to write
and obtain a new output, assuming that the UPDATE
pin is
always active. If the UPDATE
pin is not active until after the new
word has been written, it takes fourteen CLK cycles, rather than
eleven. For cases which require the output to be updated with
all of the new frequency information present, it is necessary that
the UPDATE
be inactive until after all of the new frequency
word has been written to the device. See the Timing Diagrams
for more information. The parallel registers can be written at a
rate of CLK/2, such that updated control words can be
pipelined. If the application does not require all registers to be
written, then the output frequency can be changed more
quickly. For example, if only 32 bits of frequency information are
needed and it is desired that the output be updated all at once,
then it takes four WR cycles, then the assertion low of the
UPDATE
pin, plus another fourteen CLK cycles at the DDS rate
to write and update a new frequency.
The timing is the same whether writing to the center or offset
frequency registers. For faster frequency update, consider the
ENOFR (Enable Offset Frequency Register) option. Once the
values have been written to the center and offset frequency
registers, the user can enable and disable the offset
frequency register, which is added to the center frequency
value when enabled. The ENOFR pin has a latency of
fourteen CLK cycles, but simplifies the interface because the
only pin that has to be toggled is the ENOFR pin. See “FSK
Modulation” on page 6 for a detailed explanation.
Serial Interface
A serial interface is provided for loading a tuning frequency.
This interface can be asynchronous to the master clock of the
part. When the tuning word has been shifted into the part, it is
loaded into a holding register by the serial interface clock,
SCLK. This loading triggers a synchronization circuit to transfer
the data to a slave register synchronous with the master clock.
A minimum of eleven serial clocks (at minimum serial word size
of eight) are necessary to complete the transfer to the slave
register. Another twelve DDS CLK cycles are necessary before
the output of the DDS reflects the new frequency as shown in
Equation 3.
(EQ. 1)
f
OUT
= f
CLK
x ((CF + OF +SF) mod (2
48
))/ (2
48
)
(EQ. 2)
(125 x 10
6
)/(2
48
) = 0.4µHz resolution
(EQ. 3)
Serial loading latency = ((8 x N + 3) x SCLK)+ 12 x f
CLK
ISL5314
