16
FN4901.3
January 19, 2010
Control Register Description
ADDRESS BITS DESCRIPTION
RESET
STATE
(Note 14)
0 7:0 Center frequency bits CF(7:0) (LSB). 00h
1 7:0 Center frequency bits CF(15:8). 00h
2 7:0 Center frequency bits CF(23:16). 00h
3 7:0 Center frequency bits CF(31:24). 00h
4 7:0 Center frequency bits CF(39:32). 00h
5 7:0 Center frequency bits CF(47:40) (MSB). (Reset gives
f
CLK
/4 output). 40h
6 7:0 Offset frequency bits OF(7:0) (LSB). 00h
7 7:0 Offset frequency bits OF(15:8). 00h
8 7:0 Offset frequency bits OF(23:16). 00h
9 7:0 Offset frequency bits OF(31:24). 00h
10 7:0 Offset frequency bits OF(39:32). 00h
11 7:0 Offset frequency bits OF(47:40) (MSB). 00h
12 7:0 Serial input control word. 01h
7:5 Select number of serial frequency input bits:
1xx = 40-bit word (weighting same as CF(47:8))
011 = 32-bit word (weighting same as CF(47:16))
010 = 24-bit word (weighting same as CF(47:24))
001 = 16-bit word (weighting same as CF(47:32))
000 = 8-bit word (weighting same as CF(47:40))
000b
4 Serial input sync position select:
1 = sync early. Sync is expected one serial clock period before the first data bit.
0 = sync late. Sync is expected one serial clock after the last data bit.
0b
3 Serial sync polarity: 1 = active low, 0 = active high. 0b
2 Serial clock polarity: 0 = rising edge, 1 = falling edge. 0b
1 Shift direction: 0 = MSB first, 1 = LSB first. 0b
0 Center frequency enable: 1 = enable, 0 = disable.
This bit can be used to zero the center frequency (CF(47:0)) to the phase accumulator. This does not zero
the processor interface registers—just the data path from the center frequency register to the phase
accumulator. The center frequency resets to f
CLK
/4.
1b
13 7:0 NCO control word. F8h
7 Intersil reserved. Do not change. 1b
6 Serial output frequency register enable: 1 = enable, 0 = disable.
This bit enables/disables the data path from the serial frequency register to the phase accumulator,
without changing the value of the register. Should be disabled after RESET
if not used.
1b
5 Phase accumulator feedback: 0 = accumulator feedback disabled, 1 = accumulator enabled. 1b
4:0 Intersil reserved. Do not change. 11000b
14 7:0 Test and timing control register. User must write 00h or 30h to register 14 after RESET
. 10h
5:4 NCO-to-DAC setup and hold timing control. Write either 11b or 00b to these bits. 01b
15 7:0 Register 15 does not actually exist. Any write to register 15 is an UPDATE
. This function is provided to
save one microprocessor control pin from being used for the UPDATE
pin, if the user chooses.
N/A
NOTE:
14. b = binary, h = hex
ISL5314
