MAX115CAX Datasheet MAX115CAX+T, MAX116CAX, MAX116EAX | P10-P12

MAX115/MAX116

For multichannel conversions, INT goes low after the last

channel has been digitized.

To input data into the MAX115/MAX116, pull CS low,

program the bidirectional pins A0–A3 (Table 1), and

pulse WR low. Data is latched into the devices on the

WR or CS rising edge. The ADC is now ready to convert.

Once programmed, the ADC continues operating in the

same mode until reprogrammed or until power is

removed. Figure 5 shows an example of programming a

four-channel conversion using Input Mux A.

Starting a Conversion

After programming the MAX115/MAX116 as outlined in

the Programming Modes section, pulse CONVST low to

initiate a conversion sequence. The analog inputs are

sampled at the CONVST rising edge. Do not start a

new conversion while the conversion is in progress.

Monitor the INT output. A falling edge indicates the end

of a conversion sequence.

Reading a Conversion

Digitized data from up to four channels is stored in

memory to be read out through the parallel interface.

After receiving an INT signal, the user can access up to

four conversion results by performing up to four read

operations.

With CS low, the conversion results from CH1_ are

accessed, and INT is reset high on the first RD falling

edge. On the RD rising edge, the internal address

pointer is advanced. If a single conversion is pro-

grammed, only one RD pulse is required. For multi-

channel conversions, up to four RD falling edges

sequentially access the data for channels 1 through 4.

For any number of channels converted, the address

pointer is reset to CH1_ after four RD pulses. The

address pointer also resets after receiving a CNVST

pulse. Do not perform a read operation during conver-

sion; it will corrupt the conversion’s accuracy.

__________Applications Information

Clock

The MAX115/MAX116 have an internal 10MHz (typ)

clock, which is activated by connecting CLK to DV

(internal clock startup time is 165µs typ). The CLK input

also accepts an external clock with duty cycle between

30% and 70%.

2x4-Channel, Simultaneous-Sampling

12-Bit ADCs

10 ______________________________________________________________________________________

X = Don’t care

Table 1. Modes of Operation

TO DAC

REFIN

10kΩ

0.1µF

4.7µF

= 1

2.5V

REFOUT 7

(2.5V)

MAX115

MAX116

Figure 6. Internal Reference

Input Mux A/Single-Channel Conversion (default at power-up)

Power-Down—XXX1

Input Mux B/Four-Channel Conversion81110

Input Mux B/Three-Channel Conversion60110

Input Mux B/Two-Channel Conversion41010

Input Mux B/Single-Channel Conversion20010

Input Mux A/Four-Channel Conversion

Input Mux A/Three-Channel Conversion

Input Mux A/Two-Channel Conversion

MODE

CONVERSION

TIME (µs)

100

000

A1A2A3

Internal and External Reference

The MAX115/MAX116 can be used with an internal or

external reference voltage. An external +2.5 reference

can be connected directly at REFIN. An internal buffer

with a gain of +1 provides +2.5V at REFOUT.

Internal Reference

The full-scale range with the internal reference is ±5V

for the MAX115 and ±2.5V for the MAX116. Bypass

REFIN with a 0.1µF capacitor to AGND, and bypass the

REFOUT pin with a 4.7µF (min) capacitor to AGND

(Figure 6). The maximum value to compensate the ref-

erence buffer is 22µF. Larger values are acceptable if

low-ESR capacitors are used.

External Reference

For operation over a wide temperature range, an exter-

nal +2.5V reference with tighter specifications improves

accuracy. The MAX6325 is an excellent choice

to match the MAX115/MAX116 accuracy over the

commercial and extended temperature ranges with a

1ppm/°C (max) temperature drift. Connect an external

reference at REFIN as shown in Figure 7. The minimum

impedance is 7kΩ for DC currents in both normal oper-

ation and shutdown. Bypass REFOUT with a 4.7µF low-

ESR capacitor.

Power-On Reset

When power is first applied, the internal power-on reset

(POR) circuitry activates the MAX115/MAX116 with INT

= high, ready to convert. The default conversion mode

is Input Mux A/Single Channel Conversion. See the

Programming Modes section if other configurations are

desired.

After the power supplies have been stabilized, the reset

time is 5µs. No conversions should be performed

during this phase. At power-up, data-in memory is

undefined.

Software Power-Down

Software power-down is activated by setting bit A3 of

the control word high (Table 1). It is asserted after the

WR or CS rising edge, at which point the ADC immedi-

ately powers down to a low quiescent-current state.

AVDD

and I

AVSS

drop to less than 1µA (typ), and I

DVDD

drops to 13µA (typ). The ADC circuitry and reference

buffer are turned off, but the digital interface and the

reference remain active for fast power-up recovery.

Wake up the MAX115/MAX116 by writing a control

word (A0–A3, Table 1). The bidirectional interface inter-

prets a logic zero at A3 as the start signal, and powers

up in the mode selected by A0, A1, and A2. The refer-

ence buffer’s settling time and the bypass capacitor’s

value dominate the power-up delay. With the recom-

mended 4.7µF at REFOUT, the power-up delay is typi-

cally 20ms.

Transfer Function

The MAX115/MAX116 have bipolar input ranges. Figure

8 shows the bipolar/output transfer function. Code tran-

sitions occur at successive-integer least significant bit

MAX115/MAX116

2x4-Channel, Simultaneous-Sampling

12-Bit ADCs

______________________________________________________________________________________ 11

TO DAC

REFIN

10k

4.7µF

= 1

2.5V

REFOUT 7

(2.5V)

OUT

MAX6325

MAX115

MAX116

Figure 7. External Reference

011 . . . 111

011 . . . 110

000 . . . 010

000 . . . 001

000 . . . 000

111 . . . 111

111 . . . 110

111 . . . 101

100 . . . 001

100 . . . 000

- FS

ZERO

INPUT VOLTAGE (LSB)

OUTPUT CODE

+FS - 1LSB

4096

MAX115: FS = 2 x V

REFOUT

, 1LSB = 4V

REFOUT

MAX116: FS = V

REFOUT

, 1LSB = 2V

REFOUT

4096

Figure 8. Bipolar Transfer Function

MAX115/MAX116

(LSB) values. Output coding is two-complement binary

with 1LSB = 2.44mV for the MAX115 and

1LSB = 1.22mV for the MAX116.

Output Demultiplexer

An output demultiplexer circuit is useful for isolating

data from one channel in a four-channel conversion

sequence. Figure 9’s circuit uses the external 16MHz

clock and the INT signal to generate four RD pulses

and a latch clock to save data from the desired chan-

nel. CS must be low during the four RD pulses. The

channel is selected with the binary coding of two

switches. A 16-bit 16373 latch simplifies layout.

Motor-Control Applications

Vector motor control requires monitoring of the individ-

ual phase currents. In their most basic application, the

MAX115/MAX116 simultaneously sample two currents

(CH1A and CH2A, Figure 10) and preserve the neces-

sary relative phase information. Only two of the three

phase currents have to be digitized because the third

component can be mathematically derived with a coor-

dinate transformation.

The circuit of Figure 10 shows a typical vector motor-

control application using all available inputs of the

MAX115/MAX116. CH1A and CH2A are connected

to two isolated Hall-effect current sensors and are a

2x4-Channel, Simultaneous-Sampling

12-Bit ADCs

12 ______________________________________________________________________________________

PRE

CLR

HC161

1/2 HC74

ENP

ENT

LOAD

(LSB) 0

RCO

CLR

HC688

P = Q

LATCH

CLOCK

(TO 16373 LATCH)

0CH1 0

1CH2 0

0CH3 1

1CH4 1

10kΩ

EXTERNAL

CLOCK

EXTERNAL

CLOCK

INT

Figure 9. Output Demultiplexer Circuit

P1-P3 P4-P6 P7-P9 P10-P12 P13-P14

MAX115CAX

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IC ADC 12-BIT 2X4CHAN 36-SSOP

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