MAX115CAX Datasheet MAX115CAX+T, MAX116CAX, MAX116EAX | P7-P9

MAX115/MAX116

2x4-Channel, Simultaneous-Sampling

12-Bit ADCs

_______________________________________________________________________________________ 7

MUX

2.50V

BANDGAP REFERENCE

REFIN

10kΩ

AGND REFOUT

MUX

T/H

MUX

CH1A

CH1B

CH2A

CH2B

CH3A

CH3B

CH4A

CH4B

12-BIT

DAC

CONTROL LOGIC

BUS INTERFACE

CLK CONVST INT CS RD WR DV

DGND

SAR

4x12

RAM

REF

THREE-STATE

OUTPUT

DRIVERS

AGND

D0/A2

D1/A3

D11 (MSB)

MAX115

MAX116

REF

COMP

10MHz

CLOCK

Figure 2. Functional Diagram

MAX115/MAX116

2x4-Channel, Simultaneous-Sampling

12-Bit ADCs

8 _______________________________________________________________________________________

The conversion timing and control sequences are

derived from either an internal clock or an external

clock, the CONVST signal, and the programmed mode.

The T/H amplifiers hold the input voltages at the

CONVST rising edge. Additional CONVST pulses are

ignored until the last conversion for the sample is com-

plete. An on-board sequencer converts one to four

channels per CONVST pulse. In the default mode, one

T/H output (CH1A) is converted. An interrupt signal

(INT) is provided after the last conversion is complete.

Convert two to four channels by reprogramming the

MAX115/MAX116 through the bidirectional parallel

interface. Once programmed, the MAX115/MAX116

continues to convert the specified number of channels

per CONVST pulse until they are reprogrammed. The

channels are converted sequentially, beginning with

CH1. The INT signal always follows the end of the last

conversion in a conversion sequence. The ADC con-

verts each assigned channel in 2µs and stores the

result in an internal 4 x 12-bit memory.

At the end of the last conversion, INT goes low and the

T/H amplifiers begin to track the inputs again. The data

can be accessed by applying successive pulses to the

RD pin. Successive reads access data words sequen-

tially. The memory is not random-access and data from

CH1 is always read first. After performing four consecu-

tive reads or initiating a new conversion, the address

pointer selects CH1 again. Additional read pulses cycle

through the data words. CS can be held low during

successive reads.

Input Bandwidth

The T/H’s input tracking circuitry has a 10MHz small-

signal bandwidth, so it is possible to digitize high-

speed transient events and measure periodic signals

with bandwidths exceeding the ADC’s sampling rate by

using undersampling techniques. To avoid high-

frequency signals being aliased into the frequency

band of interest, anti-alias filtering is recommended.

Analog Input Range and Input Protection

The MAX115’s input range is ±5V, and the MAX116’s

input range is ±2.5V. The input resistance for the

MAX115 is 10kΩ (typ), and the input resistance for the

MAX116 is 1MΩ (typ). An input protection structure

allows input voltages to ±17V without harming the IC.

This protection is also active in shutdown mode.

S1A S2A

HOLD

BUFFER

TRACK

HOLD

7pF

HOLD

FROM MICROSEQUENCER

REFOUT

TRACK

MUX

DAC

SAR

S1B S2B

S3B

S3A

CH_A

CH_B

MAX115

MAX116

MAX115: R1 = ∞, R2 = R3 = 5kΩ

MAX116: R1 = R2 = 5kΩ, R3 = ∞

Figure 3. Equivalent Input Circuit

Track/Holds

The MAX115/MAX116 feature four simultaneous T/Hs.

Each T/H has two multiplexed inputs. A T-switch input

configuration provides excellent hold-mode isolation.

Allow 600ns acquisition time for 12-bit accuracy.

The T/H aperture delay is typically 10ns. The 500ps

aperture-delay mismatch between the T/Hs allows the

relative phase information of up to four different inputs

to be preserved. Figure 3 shows the equivalent input

circuit, illustrating the ADC’s sampling architecture.

Only one of four T/H stages with its two multiplexed

inputs (CH_A and CH_B) is shown. All switches are in

track configuration for channel A. An internal buffer

charges the hold capacitor to minimize the required

acquisition time between conversions. The analog input

appears as a 10kΩ resistor in parallel with a 16pF

capacitor for the MAX115 and as a 1MΩ resistor in par-

allel with a 16pF capacitor for the MAX116.

Between conversions, the buffer input is connected to

channel 1 of the selected track/hold bank. When a

channel is not selected, switches S1, S2, and S3 are

placed in hold mode to improve channel-to-channel

isolation.

Digital Interface

Input data (A0–A3) and output data (D0–D11) are multi-

plexed on a three-state bidirectional interface. This par-

allel I/O can easily be interfaced with a microprocessor

(µP) or DSP. CS, WR, and RD control the write and read

operations. CS is the standard chip-select signal, which

enables the controller to address the MAX115/MAX116

as an I/O port. When CS is high, it disables the WR and

RD inputs and forces the interface into a high-Z state.

Figure 4 details the interface timing.

Programming Modes

The MAX115/MAX116 have eight conversion modes

plus power-down, which are programmed through a

bidirectional parallel interface. At power-up, the devices

default to the Input Mux A/Single-Channel Conversion

mode. The user can select between two banks (mux

inputs A or mux inputs B) of four simultaneous-sampled

input channels, as illustrated in Figure 2. An internal

microsequencer can be programmed to convert one to

four channels of the selected bank per sample. For a

single-channel conversion, CH1 is digitized, and then

INT goes low to indicate completion of the conversion.

MAX115/MAX116

2x4-Channel, Simultaneous-Sampling

12-Bit ADCs

_______________________________________________________________________________________ 9

CH1 CH2 CH3 CH4

ACQ

CONV

CWH

CRS

CRH

CWS

CONVST

INT

DATA

DATA IN

Figure 4. Timing Diagram

Figure 5. Programming a Four-Channel Conversion, Input Mux A

(LSB)

P1-P3 P4-P6 P7-P9 P10-P12 P13-P14

MAX115CAX

Mfr. #:

Buy MAX115CAX

Manufacturer:

Maxim Integrated

Description:

IC ADC 12-BIT 2X4CHAN 36-SSOP

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MAX115CAX

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