MAX115/MAX116
2x4-Channel, Simultaneous-Sampling
12-Bit ADCs
4 _______________________________________________________________________________________
CONDITIONS UNITSMIN TYP MAXSYMBOLPARAMETER
I
OUT
= 1mA V4V
OH
Output High Voltage
I
OUT
= -1.6mA V0.4V
OL
Output Low Voltage
D0–D11 µA±10Three-State Leakage Current
pF10
Three-State Output
Capacitance
V4.75 5 5.25AV
DD
Positive Supply Voltage
V-5.25 -5 -4.75AV
SS
Negative Supply Voltage
V4.75 5 5.25DV
DD
Digital Supply Voltage
mA17 25I
AVDD
Positive Supply Current
mA-20 -15I
AVSS
Negative Supply Current
mA36Digital Supply Current
µA1Shutdown Positive Current
µA-1Shutdown Negative Current
µA13Shutdown Digital Current
(Note 10) LSB±1PSRR+Positive Supply Rejection
(Note 10) LSB±1PSRR-Negative Supply Rejection
(Note 11) mW175Power Dissipation
DIGITAL OUTPUTS (D0–D11, INT)
POWER REQUIREMENTS
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD
= +5V ±5%, AV
SS
= -5V ±5%, DV
DD
= +5V ±5%, V
REFIN
= +2.5V (external reference), AGND = DGND = 0, 4.7µF capacitor
from REFOUT to AGND, 0.1µF capacitor from REFIN to AGND, f
CLK
= 16MHz, external clock, 50% duty cycle. T
A
= T
MIN
to T
MAX
,
unless otherwise noted. Typical values are at T
A
= +25°C.)
TIMING CHARACTERISTICS
(See Figure 4, AV
DD
= +5V, AV
SS
= -5V, DV
DD
= +5V, AGND = DGND = 0, T
A
= T
MIN
to T
MAX
, Typical values are at T
A
= +25°C,
unless otherwise noted.)
Guaranteed by design ns0t
CWS
CS to WR Setup Time
Guaranteed by design ns0t
CWH
CS to WR Hold Time
ns30t
WR
WR Low Pulse Width
ns30
CONDITIONS
t
AS
Address Setup Time
ns0t
AH
Address Hold Time
25pF load ns55t
ID
RD to INT Delay
ns45t
RD
Delay Time Between Reads
Guaranteed by design ns0t
CRS
CS to RD Setup Time
Guaranteed by design ns0t
CRH
CS to RD Hold Time
ns30t
RD
RD Low Pulse Width
25pF load (Note 12) ns40t
DA
Data-Access Time
25pF load (Note 13) ns545t
DH
Bus-Relinquish Time
ns30t
CW
CONVST Pulse Width
UNITSMIN TYP MAXSYMBOLPARAMETER