CY7C1347F
Document #: 38-05213 Rev. *C Page 10 of 19
Switching Characteristics Over the Operating Range
[15, 16]
Parameter Description
-250 -225 -200 -166 -133 -100
UnitMin. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
t
POWER
V
DD
(min.) to the first access
read or write
[11]
1 11111ms
t
CYC
Clock Cycle Time 4.0 4.4 5.0 6.0 7.5 10 ns
t
CH
Clock HIGH 1.7 2.0 2.0 2.5 3.0 3.5 ns
t
CL
Clock LOW 1.7 2.0 2.0 2.5 3.0 3.5 ns
t
AS
Address Set-up Before CLK
Rise
0.8 1.2 1.2 1.5 1.5 1.5 ns
t
AH
Address Hold After CLK Rise 0.4 0.5 0.5 0.5 0.5 0.5 ns
t
CO
Data Output Valid After CLK
Rise
2.6 2.6 2.8 3.5 4.0 4.5 ns
t
DOH
Data Output Hold After CLK
Rise
1.0 1.0 1.0 2.0 2.0 2.0 ns
t
WES
GW, BWS
[3:0]
Set-up Before
CLK Rise
0.8 1.2 1.2 1.5 1.5 1.5 ns
t
WEH
GW, BWS
[3:0]
Hold After CLK
Rise
0.4 0.5 0.5 0.5 0.5 0.5 ns
t
ALS
ADV/LD Set-up Before CLK
Rise
0.8 1.2 1.2 1.5 1.5 1.5 ns
t
ALH
ADV/LD Hold after CLK Rise 0.4 0.5 0.5 0.5 0.5 0.5 ns
t
DS
Data Input Set-up Before CLK
Rise
0.8 1.2 1.2 1.5 1.5 1.5 ns
t
DH
Data Input Hold After CLK
Rise
0.4 0.5 0.5 0.5 0.5 0.5 ns
t
CES
Chip Enable Set-up Before
CLK Rise
0.8 1.2 1.2 1.5 1.5 1.5 ns
t
CEH
Chip Enable Hold After CLK
Rise
0.4 0.5 0.5 0.5 0.5 0.5 ns
t
CHZ
Clock to High-Z
[12, 13, 14]
2.6 2.6 2.8 3.5 4.0 4.5 ns
t
CLZ
Clock to Low-Z
[12, 13, 14]
0 000 0 0 ns
t
EOHZ
OE HIGH to Output
High-Z
[12, 13, 14]
2.6 2.6 2.8 3.5 4.0 4.5 ns
t
EOLZ
OE LOW to Output
Low-Z
[12, 13, 14]
0 000 0 0 ns
t
EOV
OE LOW to Output Valid 2.6 2.6 2.8 3.5 4.5 4.5 ns
Notes:
11. This part has a voltage regulator internally; t
POWER
is the time that the power needs to be supplied above V
DD
(minimum) initially before a read or write operation
can be initiated.
12. t
CHZ
, t
CLZ
,t
OELZ
, and t
OEHZ
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
13. At any given voltage and temperature, t
OEHZ
is less than t
OELZ
and t
CHZ
is less than t
CLZ
to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
14. This parameter is sampled and not 100% tested.
15. Timing references level is 1.5V when V
DDQ
= 3.3V and is 1.25V when V
DDQ
= 2.5V on all data sheets.
16. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
