MAX5038/MAX5041
Dual-Phase, Parallelable, Average Current-Mode
Controllers
16 ______________________________________________________________________________________
Differential Amplifier
The differential amplifier (DIFF AMP) facilitates output
voltage remote sensing at the load (Figures 3a and 3b).
It provides true differential output voltage sensing while
rejecting the common-mode voltage errors due to high-
current ground paths. Sensing the output voltage
directly at the load provides accurate load voltage
sensing in high-current environments. The VEA pro-
vides the difference between the differential amplifier
output (DIFF) and the desired output voltage. The dif-
ferential amplifier has a bandwidth of 3MHz. The differ-
ence between SENSE+ and SENSE- regulates to the
preset output voltage for the MAX5038 and regulates to
+1V for the MAX5041.
Voltage-Error Amplifier
The VEA sets the gain of the voltage control loop and
determines the error between the differential amplifier
output and the internal reference voltage (V
REF
).
V
REF
equals V
OUT(NOM)
for the +1.8V or lower voltage
versions of the MAX5038 and V
REF
equals V
OUT(NOM)
/2
for the +2.5V and +3.3V versions. For MAX5041, V
REF
equals +1V.
An offset is added to the output voltage of the
MAX5038/MAX5041 with a finite gain (R
F
/R
IN
) of the
VEA such that the no-load output voltage is higher than
the nominal value. Choose R
F
and R
IN
from the
Adaptive Voltage Positioning section and use the follow-
ing equations to calculate the no-load output voltage.
MAX5038:
MAX5041:
where R
H
and R
L
are the feedback resistor network
(Figure 2).
Some applications require V
OUT
equal to V
OUT(NOM)
at
no load. To ensure that the output voltage does not
exceed the nominal output voltage (V
OUT(NOM)
), add a
resistor R
X
from V
CC
to EAN.
Use the following equations to calculate the value of R
X
.
For MAX5038 versions of V
OUT(NOM)
+1.8V:
For MAX5038 versions of V
OUT(NOM)
> +1.8V:
For MAX5041:
The VEA output clamps to +0.9V (plus the common-
mode voltage of +0.6V), thus limiting the average maxi-
mum current from individual phases. The maximum
average current-limit threshold for each phase is equal
to the maximum clamp voltage of the VEA divided by
the gain (18) of the current-sense amplifier. This allows
for accurate settings for the average maximum current
for each phase. Set the VEA gain using R
F
and R
IN
for
the amount of output voltage positioning required as
discussed in the Adaptive Voltage Positioning section
(Figures 3a and 3b).
Adaptive Voltage Positioning
Powering new-generation processors requires new
techniques to reduce cost, size, and power dissipation.
Voltage positioning reduces the total number of output
capacitors to meet a given transient response require-
ment. Setting the no-load output voltage slightly higher
than the output voltage during nominally loaded condi-
tions allows a larger downward voltage excursion when
the output current suddenly increases. Regulating at a
lower output voltage under a heavy load allows a larger
upward-voltage excursion when the output current sud-
denly decreases. A larger allowed, voltage-step excur-
sion reduces the required number of output capacitors
or allows for the use of higher ESR capacitors.
Voltage positioning and the ability to operate with multiple
reference voltages may require the output to regulate
away from a center value. Define the center value as the
voltage where the output drops (V
OUT
/2) at one half the
maximum output current (Figure 5).
RV
R
V
XCC
F
REF
=−×[.]16
RVV
R
V
X CC NOM
F
NOM
=− +×[( .)]212
RV V
R
V
X CC NOM
F
NOM
=− +×[( .)]06
V
R
R
RR
R
V
OUT NL
IN
F
HL
L
REF()
=+
×
+
×1
V
R
R
V
OUT NL
IN
F
OUT NOM() ( )
=+
×1
(3)
(4)
(5)
(6)
(7)
MAX5038/MAX5041
Dual-Phase, Parallelable, Average Current-Mode
Controllers
______________________________________________________________________________________ 17
Set the voltage-positioning window (V
OUT
) using the
resistive feedback of the VEA. Use the following equa-
tions to calculate the voltage-positioning window for the
MAX5038:
Use the following equation to calculate the voltage-posi-
tioning window for the MAX5041:
where R
IN
and R
F
are the input and feedback resistors of
the VEA, G
C
is the current-loop gain and R
S
is the cur-
rent-sense resistor or, if using lossless inductor current
sensing, the DC resistance of the inductor.
Phase-Locked Loop: Operation and
Compensation
The PLL synchronizes the internal oscillator to the
external frequency source when driving CLKIN.
Connecting CLKIN to V
CC
or SGND forces the PWM
frequency to default to the internal oscillator frequency
of 500kHz or 250kHz, respectively. The PLL uses a
conventional architecture consisting of a phase detec-
tor and a charge pump capable of providing 20µA of
output current. Connect an external series combination
capacitor (C25) and resistor (R4) and a parallel capaci-
tor (C26) from PLLCMP to SGND to provide frequency
compensation for the PLL (Figure 1). The pole-zero pair
compensation provides a zero at f
Z
= 1 / [R4 x (C25 +
C26)] and a pole at f
P
= 1 / (R4 x C26). Use the follow-
ing typical values for compensating the PLL:
R4 = 7.5k, C25 = 4.7nF, C26 = 470pF. If changing the
PLL frequency, expect a finite locking time of approxi-
mately 200µs.
The MAX5038/MAX5041 require compensation on
PLLCMP even when operating from the internal oscilla-
tor. The device requires an active PLL in order to gen-
erate the proper internal PWM clocks.
MOSFET Gate Drivers (DH_, DL_)
The high-side (DH_) and low-side (DL_) drivers drive
the gates of external N-channel MOSFETs (Figures 1
and 2). The drivers’ high-peak sink and source current
capability provides ample drive for the fast rise and fall
times of the switching MOSFETs. Faster rise and fall
times result in reduced cross-conduction losses. For
modern CPU voltage-regulating module applications
where the duty cycle is less than 50%, choose high-
side MOSFETs (Q1 and Q3) with a moderate R
DS(ON)
and a very low gate charge. Choose low-side
MOSFETs (Q2 and Q4) with very low R
DS(ON)
and
moderate gate charge.
The driver block also includes a logic circuit that pro-
vides an adaptive non-overlap time to prevent shoot-
through currents during transition. The typical
non-overlap time is 60ns between the high-side and
low-side MOSFETs.
BST_
V
DD
powers the low- and high-side MOSFET drivers.
Connect a 0.47µF low-ESR ceramic capacitor between
BST_ and LX_. Bypass V
CC
to PGND with 4.7µF and
0.1µF low-ESR ceramic capacitors. Reduce the PC
board area formed by these capacitors, the rectifier
diodes between V
CC
and the boost capacitor, the
MAX5038/MAX5041, and the switching MOSFETs.
G
R
C
S
=
005.
V
IR
GR
RR
R
OUT
OUT IN
CF
HL
L
=
×
××
()
×
+
2
G
R
C
S
=
005.
V
IR
GR
OUT
OUT IN
CF
=
×
××2
LOAD (A)
V
CNTR
NO LOAD
1/2 LOAD
FULL LOAD
VOLTAGE-POSITIONING W
INDOW
V
CNTR
+ V
OUT
/2
V
CNTR
- V
OUT
/2
Figure 5. Defining the Voltage-Positioning Window
(8)
(9)
(10)
(11)
MAX5038/MAX5041
Dual-Phase, Parallelable, Average Current-Mode
Controllers
18 ______________________________________________________________________________________
Overload Conditions
Average current-mode control has the ability to limit the
average current sourced by the converter during a fault
condition. When a fault condition occurs, the VEA out-
put clamps to +0.9V with respect to the common-mode
voltage (V
CM
= +0.6V) and is compared with the output
of the current-sense amplifiers (CA1 and CA2) (see
Figures 3a and 3b). The current-sense amplifier’s gain
of 18 limits the maximum current in the inductor or
sense resistor to I
LIMIT
= 50mV/R
S
.
Parallel Operation
For applications requiring large output current, parallel
up to three MAX5038/MAX5041s (six phases) to triple
the available output current. The paralleled converters
operate at the same switching frequency but different
phases keep the capacitor ripple RMS currents to a mini-
mum. Three parallel MAX5038/MAX5041 converters
deliver up to 180A of output current. To set the phase
shift of the on-board PLL, leave PHASE unconnected for
90° of phase shift (2 paralleled converters), or connect
PHASE to SGND for 60° of phase shift (3 converters in
parallel). Designate one converter as master and the
remaining converters as slaves. Connect the master and
slave controllers in a daisy-chain configuration as shown
in Figure 6. Connect CLKOUT from the master controller
to CLKIN of the first slaved controller, and CLKOUT from
the first slaved controller to CLKIN of the second slaved
controller. Choose the appropriate phase shift for mini-
mum ripple currents at the input and output capacitors.
The master controller senses the output differential volt-
age through SENSE+ and SENSE- and generates the
DIFF voltage. Disable the voltage sensing of the slaved
controllers by leaving DIFF unconnected (floating).
Figure 7 shows a detailed typical parallel application cir-
cuit using two MAX5038s. This circuit provides four
phases at an input voltage of +12V and an output volt-
age range of +1V to +3.3V at 104A.
Applications Information
Each MAX5038/MAX5041 circuit drives two 180° out-of-
phase channels. Parallel two or three MAX5038/
MAX5041 circuits to achieve four- or six-phase opera-
tion, respectively. Figure 1 shows the typical application
circuit for a two-phase operation. The design criteria for
a two-phase converter includes frequency selection,
inductor value, input/output capacitance, switching
MOSFETs, sense resistors, and the compensation net-
work. Follow the same procedure for the four- and six-
phase converter design, except for the input and output
capacitance. The input and output capacitance require-
ments vary depending on the operating duty cycle.
The examples discussed in this data sheet pertain to a
typical application with the following specifications:
V
IN
= +12V
V
OUT
= +1.8V
I
OUT(MAX)
= 52A
f
SW
= 250kHz
Peak-to-Peak Inductor Current (I
L
) = 10A
Table 1 shows a list of recommended external compo-
nents (Figure 1) and Table 2 provides component sup-
plier information.
Number of Phases
Selecting the number of phases for a voltage regulator
depends mainly on the ratio of input-to-output voltage
(operating duty cycle). Optimum output-ripple cancella-
tion depends on the right combination of operating duty
cycle and the number of phases. Use the following
equation as a starting point to choose the number of
phases:
N
PH
K/D
where K = 1, 2, or 3 and the duty cycle is D = V
OUT
/V
IN.
Choose K to make N
PH
an integer number. For exam-
ple, converting V
IN
= +12V to V
OUT
= +1.8V yields
better ripple cancellation in the six-phase converter
than in the four-phase converter. Ensure that the output
load justifies the greater number of components for
multiphase conversion. Generally limiting the maximum
output current to 25A per phase yields the most cost-
effective solution. The maximum ripple cancellation
occurs when N
PH
= K/D.
Single-phase conversion requires greater size and power
dissipation for external components such as the switch-
ing MOSFETs and the inductor. Multiphase conversion
eliminates the heatsink by distributing the power dissipa-
tion in the external components. The multiple phases
operating at given phase shifts effectively increase the
switching frequency seen by the input/output capacitors,
thereby reducing the input/output capacitance require-
ment for the same ripple performance. The lower induc-
tance value improves the large-signal response of the
converter during a transient load at the output. Consider
all these issues when determining the number of phases
necessary for the voltage regulator application.
Inductor Selection
The switching frequency per phase, peak-to-peak rip-
ple current in each phase, and allowable ripple at the
output determine the inductance value.
(12)

MAX5041EAI+T

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Manufacturer:
Maxim Integrated
Description:
Switching Controllers Dual-Phase Parallelable Average
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