MAX5038/MAX5041
Dual-Phase, Parallelable, Average Current-Mode
Controllers
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Pin Description
PIN NAME FUNCTION
1, 13
CSP2,
CSP1
Current-Sense Differential Amplifier Positive Input. Senses the inductor current. The differential voltage
between CSP_ and CSN_ is amplified internally by the current-sense amplifier gain of 18.
2, 14
CSN2,
CSN1
Current-Sense Differential Amplifier Negative Input. Senses the inductor current.
3 PHASE
Phase-Shift Setting Input. Connect PHASE to V
CC
for 120°, leave PHASE unconnected for 90°, or connect
PHASE to SGND for 60° of phase shift between the rising edges of CLKOUT and CLKIN/DH1.
4
PLLCMP
External Loop-Compensation Input. Connect compensation network for the phase lock loop (see Phase-
Locked Loop section).
5, 7
CLP2,
CLP1
Current-Error Amplifier Output. Compensate the current loop by connecting an RC network to ground.
6 SGND Signal Ground. Ground connection for the internal control circuitry.
8
SENSE+
Differential Output Voltage-Sensing Positive Input. Used to sense a remote load. Connect SENSE+ to
V
OUT+
at the load. The MAX5038 regulates the difference between SENSE+ and SENSE- according to the
factory preset output voltage. The MAX5041 regulates the SENSE+ to SENSE- difference to +1.0V.
9
SENSE-
Differential Output Voltage-Sensing Negative Input. Used to sense a remote load. Connect SENSE- to
V
OUT-
or PGND at the load.
10 DIFF Differential Remote-Sense Amplifier Output. DIFF is the output of a precision unity-gain amplifier.
11 EAN
Voltage-Error Amplifier Inverting Input. Receives the output of the differential remote-sense amplifier.
Referenced to SGND.
12
EAOUT
Voltage-Error Amplifier Output. Connect to the external gain-setting feedback resistor. The external error
amplifier gain-setting resistors determine the amount of adaptive voltage positioning
15 EN Output Enable. A logic low shuts down the power drivers. EN has an internal 5µA pullup current.
BST1,
BST2
Boost Flying-Capacitor Connection. Reservoir capacitor connection for the high-side FET driver supply.
Connect 0.47µF ceramic capacitors between BST_ and LX_.
DH1,
DH2
High-Side Gate Driver Output. Drives the gate of the high-side MOSFET.
LX1, LX2
Inductor Connection. Source connection for the high-side MOSFETs. Also serves as the return terminal for
the high-side driver.
DL1, DL2
Low-Side Gate Driver Output. Synchronous MOSFET gate drivers for the two phases.
20 V
CC
Internal +5V Regulator Output. V
CC
is derived internally from the IN voltage. Bypass to SGND with 4.7µF
and 0.1µF ceramic capacitors.
21 IN
Supply Voltage Connection. Connect IN to V
CC
for a +5V system. Connect the VRM input to IN through an
RC lowpass filter, a 2.2Ω resistor and a 0.1µF ceramic capacitor.
22 PGND
Power Ground. Connect PGND, low-side synchronous MOSFET’s source, and V
CC
bypass capacitor
returns together.
27
CLKOUT
Oscillator Output. CLKOUT is phase-shifted from CLKIN by the amount specified by PHASE. Use CLKOUT
to parallel additional MAX5038/MAX5041s.
28 CLKIN
CMOS Logic Clock Input. Drive the internal oscillator with a frequency range between 125kHz and 600kHz.
The PWM frequency defaults to the internal oscillator if CLKIN is connected to V
CC
or SGND. Connect
CLKIN to SGND to set the internal oscillator to 250kHz or connect to V
CC
to set the internal oscillator to
500kHz. CLKIN has an internal 5µA pulldown current.
