NCP81071
www.onsemi.com
11
LAYOUT GUIDELINES
The switching performance of NCP81071 highly depends
on the design of PCB board. The following layout design
guidelines are recommended when designing boards using
these high speed drivers.
Place the driver as close as possible to the driven
MOSFET.
Place the bypass capacitor between VDD and GND as
close as possible to the driver to improve the noise filtering.
It is preferred to use low inductance components such as
chip capacitor and chip resistor. If vias are used, connect
several paralleled vias to reduce the inductance of the vias.
Minimize the turn-on/sourcing current and
turn-off/sinking current paths in order to minimize stray
inductance. Otherwise high di/dt established in these loops
with stray inductance can induce significant voltage spikes
on the output of the driver and MOSFET Gate terminal.
Keep power loops as short as possible by paralleling the
source and return traces (flux cancellation).
Keep low level signal lines away from high level power
lines with a lot of switching noise.
Place a ground plane for better noise shielding. Beside
noise shielding, ground plane is also useful for heat
dissipation.
NCP81071 DFN and MSOP package have thermal pad
for: 1) quiet GND for all the driver circuits; 2) heat sink for
the driver. This pad must be connected to a ground plane and
no switching currents from the driven MOSFET should pass
through the ground plane under the driver. To maximize the
heatsinking capability, it is recommended several ground
layers are added to connect to the ground plane and thermal
pad. A via array within the area of package can conduct the
heat from the package to the ground layers and the whole
PCB board. The number of vias and the size of ground plane
are determined by the power dissipation of NCP81071
(VDD voltage, switching frequency and load condition), the
air flow condition and its maximum junction temperature.
ORDERING INFORMATION
Part Number Output Configuration Temperature Range (5C) Package Type Shipping
†
NCP81071ADR2G dual inverting
−40 to +140
SOIC−8
(Pb−Free)
2500 / Tape & Reel
NCP81071BDR2G dual non inverting
NCP81071CDR2G One inverting
one non inverting
NCP81071AZR2G dual inverting
MSOP8 EP
(Pb−Free)
3000 / Tape & Reel
NCP81071BZR2G dual non inverting
NCP81071CZR2G One inverting
one non inverting
NCP81071AMNTXG dual inverting
WDFN8
(Pb−Free)
3000 / Tape & Reel
NCP81071BMNTXG dual non inverting
NCP81071CMNTXG One inverting
one non inverting
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
