6
Serial Interface Timing Information
Parameter Symbol Minimum Maximum Units
SCL Clock Frequency f
scl
0 100 kHz
(Repeated) START Condition Hold Time t
HD:STA
4 - µs
Data Hold Time t
HD:CAT
0 3.45 µs
SCL Clock Low Period t
LOW
4.7 - µs
SCL Clock High Period t
HIGH
4.0 - µs
Repeated START Condition Setup Time t
SU:STA
4.7 - µs
Data Setup Time t
SU:DAT
250 - µs
STOP Condition Setup Time t
SU:STD
4.0 - µs
Bus Free Time Between START and STOP Conditions t
BUF
4.7 - µs
Figure 2. Serial interface bus timing waveforms
Serial Interface Reference
Description
The programming interface to the ADJD-S371-QR999 is
a 2-wire serial bus. The bus consists of a serial clock (SCL)
and a serial data (SDA) line. The SDA line is bi-directional
on ADJD-S371-QR999 and must be connected through
a pull-up resistor to the positive power supply. When the
bus is free, both lines are HIGH.
The 2-wire serial bus on ADJD-S371-QR999 requires one
device to act as a master while all other devices must be
slaves. A master is a device that initiates a data transfer
on the bus, generates the clock signal and terminates
the data transfer while a device addressed by the master
is called a slave. Slaves are identied by unique device
addresses.
Both master and slave can act as a transmitter or a
receiver but the master controls the direction for data
transfer. A transmitter is a device that sends data to the
bus and a receiver is a device that receives data from
the bus.
The ADJD-S371-QR999 serial bus interface always oper-
ates as a slave transceiver with a data transfer rate of up
to 100kbit/s.
START/STOP Condition
The master initiates and terminates all serial data
transfers. To begin a serial data transfer, the master must
send a unique signal to the bus called a START condition.
This is dened as a HIGH to LOW transition on the SDA
line while SCL is HIGH.
t
LOW
t
HD:DAT
t
HD:STA
t
SU:STO
t
HIGH
t
SU:DAT
t
HD:STA
t
BUF
t
SU:STA
SDA
SCL
S Sr P S
