ADJD-S371-QR999

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The bus is considered to be busy after a START (S)

condition. It will be considered free a certain time after

functionally identical.

Figure 3. START/STOP condition

Data Transfer

The master initiates data transfer after a START condition.

Data is transferred in bits with the master generating

one clock pulse for each bit sent. For a data bit to be

valid, the SDA data line must be stable during the HIGH

period of the SCL clock line. Only during the LOW period

of the SCL clock line can the SDA data line change state

to either HIGH or LOW.

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minimum timing requirements.

The master by default drives the SDA data line. The

slave drives the SDA data line only when sending an

acknowledge bit after the master writes data to the

data.

example of a master implementation and how the SCL

clock line and SDA data line can be synchronized.

Figure 5. Data bit synchronization

A complete data transfer is 8-bits long or 1-byte. Each

byte is sent most signicant bit (MSB) rst followed by

an acknowledge or not acknowledge bit. Each data

transfer can send an unlimited number of bytes

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The receiver must always acknowledge each byte sent

in a data transfer. In the case of the slave-receiver and

master-transmitter, if the slave-receiver does not send

an acknowledge bit, the master-transmitter can either

STOP the transfer or generate a repeated START to start

condition to begin a new data transfer.

In all cases, the master generates the acknowledge or

not acknowledge SCL clock pulse.

Figure 8. Master-receiver acknowledge