8 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
12/15/2011
IS61LV25616AL
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,3)
(Over Operating Range)
-10 -12
Symbol Parameter Min. Max. Min. Max. Unit
twc Write Cycle Time 10 — 12 — ns
tsce CE to Write End 8 — 8 — ns
taw Address Setup Time to Write End 8 — 8 — ns
tHa Address Hold from Write End 0 — 0 — ns
tsa Address Setup Time 0 — 0 — ns
tPwb LB, UB Valid to End of Write 8 — 8 — ns
tPwe1 WE Pulse Width 8 — 8 — ns
tPwe2 WE Pulse Width (OE = LOW) 10 — 12 — ns
tsD Data Setup to Write End 6 — 6 — ns
tHD Data Hold from Write End 0 — 0 — ns
tHzwe
(2)
WE LOW to High-Z Output — 5 — 6 ns
tLzwe
(2)
WE HIGH to Low-Z Output 2 — 2 — ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V
to 3.0V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and UB or LB and WE LOW. All signals must be in valid
states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing
are referenced to the rising or falling edge of the signal that terminates the write.
tRC
t
OHA
tAA
tDOE
tLZOE
tACE
tLZCE
tHZOE
HIGH-Z
DATA VALID
UB_CEDR2.eps
tHZB
ADDRESS
OE
CE
LB, UB
D
OUT
t
HZCE
tBA
tLZB
tRC
tPD
ISB
ICC
50%
V
DD
Supply
Current
50%
tPU
READ CYCLE NO. 2
(1,3)
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE, UB, or LB =
VIL.
3. Address is valid prior to or coincident with CE LOW transition.
