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74LVT16374AEVK

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
74LVT_LVTH16374A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 10 — 2 April 2012 6 of 19
NXP Semiconductors
74LVT16374A; 74LVTH16374A
3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
7. Limiting values
[1] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
[2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability.
[3] Above 60 C the value of P
tot
derates linearly with 5.5 mW/K.
[4] Above 70 C the value of P
tot
derates linearly with 1.8 mW/K.
8. Recommended operating conditions
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
V
CC
supply voltage 0.5 +4.6 V
V
I
input voltage
[1]
0.5 +7.0 V
V
O
output voltage output in OFF-state or
HIGH-state
[1]
0.5 +7.0 V
I
IK
input clamping current V
I
< 0 V 50 - mA
I
OK
output clamping current V
O
< 0 V 50 - mA
I
O
output current output in LOW-state - 128 mA
output in HIGH-state 64 - mA
T
stg
storage temperature 65 +150 C
T
j
junction temperature
[2]
- 150 C
P
tot
total power dissipation T
amb
= 40 C to +85 C
(T)SSOP48 package
[3]
- 500 mW
VFBGA56 and HXQFN60
package
[4]
- 1000 mW
Table 5. Recommended operating conditions
Symbol Parameter Conditions Min Typ Max Unit
V
CC
supply voltage 2.7 - 3.6 V
V
I
input voltage 0 - 5.5 V
V
IH
HIGH-level input voltage 2.0 - - V
V
IL
LOW-level input voltage - - 0.8 V
I
OH
HIGH-level output current 32 - - mA
I
OL
LOW-level output current none - - 32 mA
current duty cycle 50 %;
f
i
1kHz
--64mA
T
amb
ambient temperature in free-air 40 - +85 C
t/V input transition rise and fall rate outputs enabled - - 10 ns/V
74LVT_LVTH16374A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 10 — 2 April 2012 7 of 19
NXP Semiconductors
74LVT16374A; 74LVTH16374A
3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
9. Static characteristics
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ
[1]
Max Unit
T
amb
= 40 C to +85 C
V
IK
input clamping voltage V
CC
= 2.7 V; I
IK
= 18 mA 1.2 0.85 - V
V
OH
HIGH-level output voltage I
OH
= 100 A; V
CC
= 2.7 V to 3.6 V V
CC
0.2 V
CC
-V
I
OH
= 8mA; V
CC
= 2.7 V 2.4 2.5 - V
I
OH
= 32 mA; V
CC
= 3.0 V 2.0 2.3 - V
V
OL
LOW-level output voltage V
CC
= 2.7 V
I
OL
= 100 A - 0.07 0.2 V
I
OL
= 24 mA - 0.3 0.5 V
V
CC
= 3.0 V
I
OL
= 16 mA - 0.25 0.4 V
I
OL
= 32 mA - 0.3 0.5 V
I
OL
= 64 mA - 0.4 0.55 V
V
OL(pu)
power-up LOW-level
output voltage
V
CC
= 3.6 V; I
O
= 1 mA; V
I
= V
CC
or GND
[2]
- 0.1 0.55 V
I
I
input leakage current control pins
V
CC
= 3.6 V; V
I
= V
CC
or GND - 0.1 1 A
V
CC
= 0 V or 3.6 V; V
I
= 5.5 V - 0.4 10 A
input data pins
[3]
V
CC
= 0 V or 3.6 V; V
I
= 5.5 V - 0.4 10 A
V
CC
= 3.6 V; V
I
= V
CC
-0.11A
V
CC
= 3.6 V; V
I
= 0 V 5 0.4 - A
I
OFF
power-off leakage current V
CC
= 0 V; V
I
or V
O
= 0V to4.5V - 0.1 100 A
I
BHL
bus hold LOW current V
CC
= 3 V; V
I
= 0.8 V 75 135 - A
I
BHH
bus hold HIGH current V
CC
= 3 V; V
I
= 2.0 V - 135 75 A
I
BHLO
bus hold LOW
overdrive current
input data pins;
V
I
=0Vto3.6V;V
CC
=3.6V
[4]
500 - - A
I
BHHO
bus hold HIGH
overdrive current
input data pins;
V
I
=0Vto3.6V;V
CC
=3.6V
[4]
--500 A
I
LO
output leakage current output in HIGH-state when V
O
>V
CC
;
V
O
= 5.5 V; V
CC
=3.0V
- 50 125 A
I
O(pu/pd)
power-up/power-down
output current
V
CC
1.2 V; V
O
= 0.5 V to V
CC
; V
I
= GND or
V
CC
; nOE = don’t care
[5]
-1100 A
I
OZ
OFF-state output current V
CC
= 3.6 V; V
I
= V
IH
or V
IL
output HIGH: V
O
= 3.0 V - 0.5 5 A
output LOW: V
O
= 0.5 V 50.5-A
I
CC
supply current V
CC
= 3.6 V; V
I
= GND or V
CC
; I
O
=0A
outputs HIGH - 0.07 0.12 mA
outputs LOW - 4.0 6.0 mA
outputs disabled
[6]
- 0.07 0.12 mA
74LVT_LVTH16374A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 10 — 2 April 2012 8 of 19
NXP Semiconductors
74LVT16374A; 74LVTH16374A
3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
[1] Typical values are measured at V
CC
= 3.3 V and at T
amb
= 25 C.
[2] For valid test results, data must not be loaded into the flips-flops (or latches) after applying power.
[3] Unused pins at V
CC
or GND.
[4] This is the bus hold overdrive current required to force the input to the opposite logic state.
[5] This parameter is valid for any V
CC
between 0 V and 1.2 V with a transition time of up to 10 ms. From V
CC
= 1.2 V to V
CC
= 3.3 V 0.3 V
a transition time of 100 s is permitted. This parameter is valid for T
amb
= 25 C only.
[6] I
CC
is measured with outputs pulled to V
CC
or GND.
[7] This is the increase in supply current for each input at the specified voltage level other than V
CC
or GND.
10. Dynamic characteristics
I
CC
additional supply current per input pin; V
CC
= 3.0 V to 3.6 V; one input
at V
CC
0.6 V, other inputs at V
CC
or GND
[7]
-0.10.2mA
C
I
input capacitance input pins; V
I
= 0 V or 3.0 V - 3 - pF
C
O
output capacitance output pins nQn; outputs disabled;
V
O
=0VorV
CC
-9-pF
Table 6. Static characteristics
…continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ
[1]
Max Unit
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 10
.
Symbol Parameter Conditions Min Typ
[1]
Max Unit
T
amb
= 40 C to +85 C
f
max
maximum frequency nCP; V
CC
= 3.3 V 0.3 V; see Figure 7 150 - - MHz
t
PLH
LOW to HIGH
propagation delay
nCP to nQn; see Figure 7
V
CC
= 3.3 V 0.3 V 1.5 2.9 5.0 ns
V
CC
= 2.7 V - - 5.6 ns
t
PHL
HIGH to LOW
propagation delay
nCP to nQn; see Figure 7
V
CC
= 3.3 V 0.3 V 1.5 3.0 5.0 ns
V
CC
= 2.7 V - - 5.6 ns
t
PZH
OFF-state to HIGH
propagation delay
nOE to nQn; see Figure 8
V
CC
= 3.3 V 0.3 V 1.5 3.2 4.8 ns
V
CC
= 2.7 V - - 6.0 ns
t
PZL
OFF-state to LOW
propagation delay
nOE to nQn; see Figure 8
V
CC
= 3.3 V 0.3 V 1.5 3.0 4.6 ns
V
CC
= 2.7 V - - 5.2 ns
t
PHZ
HIGH to OFF-state
propagation delay
nOE to nQn; see Figure 8
V
CC
= 3.3 V 0.3 V 1.5 3.9 5.4 ns
V
CC
= 2.7 V - - 6.0 ns
t
PLZ
LOW to OFF-state
propagation delay
nOE to nQn; see Figure 8
V
CC
= 3.3 V 0.3 V 1.5 3.4 4.6 ns
V
CC
= 2.7 V - - 5.0 ns
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74LVT16374AEVK

Mfr. #:
Buy 74LVT16374AEVK
Manufacturer:
Nexperia
Description:
Flip Flops 74LVT16374AEV/VFBGA56/STANDARD
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