DC and AC parameters M24512-x, M24256-Bx
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Table 17. 1 MHz AC characteristics (M24xxx-HR, see Table 9 and Table 11 )
Test conditions specified in Table 9
Symbol Alt. Parameter Min. Max. Unit
f
C
f
SCL
Clock frequency 0 1 MHz
t
CHCL
t
HIGH
Clock pulse width high 300 - ns
t
CLCH
t
LOW
Clock pulse width low 400 - ns
t
XH1XH2
(1)
1. Values recommended by the I²C-bus Fast-Mode specification.
t
R
Input signal rise time 20 300 ns
t
XL1XL2
(1)
t
F
Input signal fall time 20 300 ns
t
DL1DL2
(2)
2. Characterized only, not tested in production.
t
F
SDA (out) fall time 20 100 ns
t
DXCX
t
SU:DAT
Data in setup time 80 - ns
t
CLDX
t
HD:DAT
Data in hold time 0 - ns
t
CLQX
t
DH
Data out hold time 50 - ns
t
CLQV
(3)(4)
3. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
4. t
CLQV
is the time (from the falling edge of SCL) required by the SDA bus line to reach 0.8V
CC
, assuming
that the R
bus
× C
bus
time constant is less than 150 ns (as specified in Figure 5).
t
AA
Clock low to next data valid (access time) 50 500 ns
t
CHDX
(5)
5. For a reStart condition, or following a Write cycle.
t
SU:STA
Start condition setup time 250 - ns
t
DLCL
t
HD:STA
Start condition hold time 250 - ns
t
CHDH
t
SU:STO
Stop condition setup time 250 - ns
t
DHDL
t
BUF
Time between Stop condition and next
Start condition
500 - ns
t
W
t
WR
Write time - 5 ms
t
NS
(2)
Pulse width ignored (input filter on SCL and
SDA)
-50ns
