IS61/64WV204816ALL
IS61/64WV204816BLL
Integrated Silicon Solution, Inc.- www.issi.com 10
Rev. 0B
06/22/2016
WRITE CYCLE AC CHARACTERISTICS
Address Setup Time to Write End
Address Hold from Write End
WE# Pulse Width (OE# = LOW)
Notes:
1 The internal write time is defined by the overlap of CS# = LOW, UB# or LB# = LOW, and WE# = LOW. All conditions must be in valid states
to initiate a Write, but any condition can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.
2 Tested tPWE > tHZWE + tSD when OE# is LOW.
AC WAVEFORMS
WRITE CYCLE NO. 1 (CS# CONTROLLED, OE# = HIGH OR LOW)
ADDRESS
CS#
WE#
UB#,LB#
DOUT
DIN
tWC
tHA
tAW
tPWE
tPWB
tSA
tHZWE
tLZWE
tSD
tHD
DATA IN VALID
DATA UNDEFINED
HIGH-Z
DATA UNDEFINED
tSCS
(1)
(2)
Note:
1. tHZWE is is based on the assumption when tSA=0nS after READ operation. Actual DOUT for tHZWE may not appear if OE# goes high before
Write Cycle.