IS61WV204816BLL-10BLI

IS61/64WV204816ALL
IS61/64WV204816BLL
Integrated Silicon Solution, Inc.- www.issi.com 7
Rev. 0B
06/22/2016
POWER SUPPLY CHARACTERISTICS-II FOR POWER
(1, 2)
(OVER THE OPERATING RANGE)
Symbol
Parameter
Test Conditions
Grade
-10
Max.
-12
Max.
Unit
ICC
V
DD
Dynamic Operating
Supply Current
V
DD
= MAX, I
OU T
= 0 mA, f = f
MAX
Com.
90
85
mA
Ind.
100
95
Auto.
140
135
ICC1
Operating Supply Current
V
DD
= MAX,
I
OUT
= 0 mA, f = 0
Com.
80
80
mA
Ind.
90
90
Auto.
110
110
ISB1
TTL Standby Current
(TTL Inputs)
V
DD
= MAX,
V
IN =
V
IH
or V
IL
V
IH ,
f = 0
Com.
60
60
mA
Ind.
70
70
Auto.
80
80
ISB2
CMOS Standby Current
(CMOS Inputs)
V
DD
= MAX,
V
DD
- 0.2V
V
IN
V
DD
- 0.2V
,
or
V
IN
0.2V
, f = 0
Com.
50
50
mA
Ind.
60
60
Auto.
70
70
Typ.
(2)
10
Notes:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input line change.
2. Typical values are measured at VDD = 3.0V/1.8V, TA = 25 °C and not 100% tested.
IS61/64WV204816ALL
IS61/64WV204816BLL
Integrated Silicon Solution, Inc.- www.issi.com 8
Rev. 0B
06/22/2016
AC CHARACTERISTICS
(OVER OPERATING RANGE)
READ CYCLE AC CHARACTERISTICS
Parameter
Symbol
-10
(1)
-12
(1)
unit
notes
Min
Min
Min
Max
Read Cycle Time
tRC
10
-
12
-
ns
Address Access Time
tAA
-
10
-
12
ns
Output Hold Time
tOHA
2.5
-
2.5
-
ns
CS# Access Time
tACE
-
10
-
12
ns
OE# Access Time
tDOE
-
6
-
7
ns
OE# to High-Z Output
tHZOE
0
5
0
6
ns
2
OE# to Low-Z Output
tLZOE
0
-
0
-
ns
2
CS# to High-Z Output
tHZCE
0
5
0
6
ns
2
CS# to Low-Z Output
tLZCE
3
-
3
-
ns
2
UB#, LB# Access Time
tBA
-
6
-
7
ns
UB#, LB# to High-Z Output
tHZB
0
5
0
6
ns
2
UB#, LB# to Low-Z Output
tLZB
0
-
0
-
ns
2
Notes:
1. Test conditions assume signal transition times of 1.5 ns or less, timing reference levels of V
DD
/2, input pulse levels of 0V to V
DD
and output
loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
IS61/64WV204816ALL
IS61/64WV204816BLL
Integrated Silicon Solution, Inc.- www.issi.com 9
Rev. 0B
06/22/2016
AC WAVEFORMS
READ CYCLE NO. 1
(1)
(Address Controlled, CS# = OE# = UB# = LB# = LOW, WE# = HIGH)
tRC
Address
DQ 0-15
tOHA
tOHA
tAA
PREVIOUS DATA VALID DATA VALID
Note:
1. The device is continuously selected.
READ CYCLE NO. 2
(1)
(OE# CONTROLLED, WE# = HIGH)
OE#
CS#
DOUT
tAA
ADDRESS
tRC
tOHA
tDOE
tLZOE
tACS
tLZCS
tHZOE
tHZCS
HIGH-Z
DATA VALID
tLZB
tHZB
tBA
UB#,LB#
LOW-Z
Note:
1. Address is valid prior to or coincident with CS# LOW transition.

IS61WV204816BLL-10BLI

Mfr. #:
Manufacturer:
ISSI
Description:
SRAM 32Mb High-Speed Async 1Mbx16 10ns
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