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LTC1148CS#TRPBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
10
LTC1148
LTC1148-3.3/LTC1148-5
114835fd
APPLICATIO S I FOR ATIO
WUU U
level threshold MOSFETs (V
GS(TH)
< 2.5V) are strongly
recommended. The LTC1148/LTC1148HV series supply
voltage must always be less than the absolute maximum
V
GS
ratings for the MOSFETs.
The maximum output current I
MAX
determines the R
DS(ON)
requirement for the two MOSFETs. When the LTC1148
series is operating in continuous mode, the simplifying
assumption can be made that one of the two MOSFETs is
always conducting the average load current. The duty
cycles for the two MOSFETs are given by:
P-Ch Duty Cycle =
V
OUT
V
IN
N-Ch Duty Cycle =
(V
IN
– V
OUT
)
V
IN
From the duty cycles the required R
DS(ON)
for each MOS-
FET can be derived:
P-Ch R
DS(ON)
=
V
IN
(P
P
)
V
OUT
(I
MAX
2
)(1 + δ
P
)
N-Ch R
DS(ON)
=
V
IN
(P
N
)
(V
IN
– V
OUT
)(I
MAX
2
)(1 + δ
N
)
where P
P
and P
N
are the allowable power dissipations and
d
P
and d
N
are the temperature dependencies of R
DS(ON)
.
P
P
and P
N
will be determined by efficiency and/or thermal
requirements (see Efficiency Considerations). (1 + d) is
generally given for a MOSFET in the form of a normalized
R
DS(ON)
vs temperature curve, but d = 0.007/°C can be
used as an approximation for low voltage MOSFETs.
The Schottky diode D1 shown in Figure 1 only conducts
during the dead-time between the conduction of the two
power MOSFETs. D1’s sole purpose in life is to prevent the
body diode of the N-channel MOSFET from turning on and
storing charge during the dead time, which could cost as
much as 1% in efficiency (although there are no other
harmful effects if D1 is omitted). Therefore, D1 should be
selected for a forward voltage of less than 0.7V when
conducting I
MAX
.
C
IN
and C
OUT
Selection
In continuous mode, the source of the P-channel MOSFET
is a square wave of duty cycle V
OUT
/V
IN
. To prevent large
voltage transients, a low ESR input capacitor sized for the
maximum RMS current must be used. The maximum
RMS capacitor current is given by:
C
IN
Required I
RMS
≈ I
MAX
[V
OUT
(V
IN
–
V
OUT
)]
1/2
V
IN
This formula has a maximum at V
IN
= 2V
OUT
, where
I
RMS
= I
OUT
/2. This simple worst-case condition is com-
monly used for design because even significant devia-
tions do not offer much relief. Note that capacitor
manufacturer’s ripple current ratings are often based on
only 2000 hours of life. This makes it advisable to further
derate the capacitor, or to choose a capacitor rated at a
higher temperature than required. Always consult the
manufacturer if there is any question. An additional 0.1µF
to 1µF ceramic capacitor is also required on V
IN
Pin 3 for
high frequency decoupling.
The selection of C
OUT
is driven by the required effective
series resistance (ESR).
The ESR of C
OUT
must be less
than twice the value of R
SENSE
for proper operation of the
LTC1148 series:
C
OUT
Required ESR < 2R
SENSE
Optimum efficiency is obtained by making the ESR equal
to R
SENSE
. As the ESR is increased up to 2R
SENSE
, the
efficiency degrades by less than 1%. If the ESR is greater
than 2R
SENSE
, the voltage ripple on the output capacitor
will prematurely trigger Burst Mode
operation, resulting in
disruption of continuous mode and an efficiency hit which
can be several percent.
Manufacturers such as Nichicon and United Chemicon
should be considered for high performance capacitors.
The OS-CON semiconductor dielectric capacitor available
from Sanyo has the lowest ESR/size ratio of any aluminum
electrolytic at a somewhat higher price. Once the ESR
requirement for C
OUT
has been met, the RMS current
rating generally far exceeds the I
RIPPLE(P-P)
requirement.
11
LTC1148
LTC1148-3.3/LTC1148-5
114835fd
APPLICATIO S I FOR ATIO
WUU U
In surface mount applications multiple capacitors may
have to be paralleled to meet the capacitance, ESR, or
RMS current handling requirements of the application.
Aluminum electrolytic and dry tantalum capacitors are
both available in surface mount configurations. In the
case of tantalum, it is critical that the capacitors are surge
tested for use in switching power supplies. An excellent
choice is the AVX TPS series of surface mount tantalums,
available in case heights ranging from 2mm to 4mm. For
example, if 200µF/10V is called for in an application
requiring 3mm height, two AVX 100µF/10V (P/N TPSD
107K010) could be used. Consult the manufacturer for
other specific recommendations.
At low supply voltages, a minimum capacitance at C
OUT
is needed to prevent an abnormal low frequency oper-
ating mode (see Figure 4). When C
OUT
is made too
small, the output ripple at low frequencies will be large
enough to trip the voltage comparator. This causes
Burst Mode
operation to be activated when the LTC1148
series would normally be in continuous operation. The
effect is most pronounced with low values of R
SENSE
and can be improved by operating at higher frequencies
with lower values of L. The output remains in regulation
at all times.
several cycles to respond to a step in DC (resistive) load
current. When a load step occurs, V
OUT
shifts by an
amount equal to ∆I
LOAD
• ESR, where ESR is the effective
series resistance of C
OUT
. ∆I
LOAD
also begins to charge
or discharge C
OUT
until the regulator loop adapts to the
current change and returns V
OUT
to its steady state
value. During this recovery time V
OUT
can be monitored
for overshoot or ringing which would indicate a stability
problem. The Pin 6 external components shown in the
Figure 1 circuit will prove adequate compensation for
most applications.
A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C
OUT
, causing a rapid drop in V
OUT
. No regulator can
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately 25
•
C
LOAD
.
Thus a 10µF capacitor would require a 250µs rise time,
limiting the charging current to about 200mA.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can be
expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc., are the individual losses as a percent-
age of input power. (For high efficiency circuits only small
errors are incurred by expressing losses as a percentage
of output power).
Although all dissipative elements in the circuit produce
losses, three main sources usually account for most of the
losses in LTC1148 series circuits: 1) LTC1148 DC bias
current, 2) MOSFET gate charge current, and 3) I
2
R
losses.
1. The DC supply current is the current which flows into
V
IN
Pin 3 less the gate charge current. For V
IN
= 10V the
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
(V
IN
– V
OUT
) VOLTAGE (V)
0
C
OUT
(µF)
600
1000
4
LTC1148 • F04
400
200
0
1
2
3
5
800
L = 50µH
R
SENSE
= 0.02Ω
L = 25µH
R
SENSE
= 0.02Ω
L = 50µH
R
SENSE
= 0.05Ω
Figure 4. Minimum Value of C
OUT
12
LTC1148
LTC1148-3.3/LTC1148-5
114835fd
APPLICATIO S I FOR ATIO
WUU U
LTC1148 DC supply current is 160µA for no load, and
increases proportionally with load up to a constant
1.6mA after the LTC1148 series has entered continu-
ous mode. Because the DC bias current is drawn from
V
IN
, the resulting loss increases with input voltage. For
V
IN
= 10V the DC bias losses are generally less than 1%
for load currents over 30mA. However, at very low load
currents the DC bias current accounts for nearly all of
the loss.
2. MOSFET gate charge current results from switching the
gate capacitance of the power MOSFETs. Each time a
MOSFET gate is switched from low to high to low again,
a packet of charge dQ moves from V
IN
to ground. The
resulting dQ/dt is a current out of V
IN
which is typically
much larger than the DC supply current. In continuous
mode, I
GATECHG
= f (Q
N
+ Q
P
). The typical gate charge
for a 0.1Ω N-channel power MOSFET is 25nC, and for
a P-channel about twice that value. This results in
I
GATECHG
= 7.5mA in 100kHz continuous operation, for
a 2% to 3% typical mid-current loss with V
IN
= 10V.
Note that the gate charge loss increases directly with
both input voltage and operating frequency. This is the
principal reason why the highest efficiency circuits
operate at moderate frequencies. Furthermore, it ar-
gues against using larger MOSFETs than necessary to
control I
2
R losses, since overkill can cost efficiency as
well as money!
3. I
2
R losses are easily predicted from the DC resistances
of the MOSFET, inductor, and current shunt. In continu-
ous mode the average output current flows through L
and R
SENSE
, but is “chopped” between the P-channel
and N-channel MOSFETs. If the two MOSFETs have
approximately the same R
DS(ON)
, then the resistance of
one MOSFET can simply be summed with the resis-
tances of L and R
SENSE
to obtain I
2
R losses. For
example, if each R
DS(ON)
= 0.1Ω, R
L
= 0.15Ω, and
R
SENSE
= 0.05Ω, then the total resistance is 0.3Ω. This
results in losses ranging from 3% to 12% as the output
current increases from 0.5A to 2A. I
2
R losses cause the
efficiency to roll-off at high output currents.
Figure 5 shows how the efficiency losses in a typical
LTC1148 series regulator end up being apportioned.
Figure 5. Efficiency Loss
OUTPUT CURRENT (A)
0.01
EFFICIENCY/LOSS (%)
90
95
1
LTC1148 • F05
85
80
0.03
0.1
0.3
3
100
GATE CHARGE
LTC1148 I
Q
I
2
R
The gate charge loss is responsible for the majority of
the efficiency lost in the mid-current region. If Burst
Mode operation was not employed at low currents, the
gate charge loss alone would cause efficiency to drop to
unacceptable levels. With Burst Mode
operation, the
DC supply current represents the lone (and unavoid-
able) loss component which continues to become a
higher percentage as output current is reduced. As
expected, the I
2
R losses dominate at high load currents.
Other losses including C
IN
and C
OUT
ESR dissipative
losses, MOSFET switching losses, Schottky conduction
losses during dead time, and inductor core losses, gener-
ally account for less than 2% total additional loss.
Design Example
As a design example, assume V
IN
= 12V (nominal),
V
OUT
= 5V, I
MAX
= 2A, and f = 200kHz; R
SENSE
, C
T
and L
can immediately be calculated:
R
SENSE
= 100mV/2 = 0.05Ω
t
OFF
= (1/200kHz)[1 – (5/12)] = 2.92µs
C
T
= 2.92µs/[(1.3)(10
4
)] = 220pF
L
MIN
= 5.1
(
10
5
)0.05Ω(220pF)5V = 28µH
Assume that the MOSFET dissipations are to be limited to
P
N
= P
P
= 250mW.
If T
A
= 50°C and the thermal resistance of each MOSFET
is 50°C/W, then the junction temperatures will be 63°C
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LTC1148CS#TRPBF

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Manufacturer:
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Description:
Switching Voltage Regulators Hi Eff Sync Buck Sw Regs
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