13
LTC1148
LTC1148-3.3/LTC1148-5
114835fd
APPLICATIO S I FOR ATIO
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To prevent stray pickup a 100pF capacitor is suggested
across R1 located close to the LTC1148.
For Figure 1 applications with V
OUT
below 2V, or when
R
SENSE
is moved to ground, the current sense comparator
inputs operate near ground. When the current comparator
is operated at less than 2V common mode, the off time
increases approximately 40%, requiring the use of a
smaller timing capacitor C
T
.
Auxiliary Windings – Suppressing Burst Mode
Operation
The LTC1148 synchronous switch removes the normal
limitation that power must be drawn from the inductor
primary winding in order to extract power from auxil-
iary windings. With synchronous switching, auxiliary
outputs may be loaded without regard to the primary
output load, providing that the loop remains in continu-
ous mode operation.
Burst Mode
operation can be suppressed at low output
currents with a simple external network which cancels the
25mV minimum current comparator threshold. This tech-
nique is also useful for eliminating audible noise from
certain types of inductors in high current (I
OUT
> 5A)
applications when they are lightly loaded.
An external offset is put in series with the SENSE
pin to
subtract from the built-in 25mV offset. An example of this
technique is shown in Figure 6. Two 100 resistors are
inserted in series with the leads from the sense resistor.
and δ
P
= δ
N
= 0.007(63 – 25) = 0.27. The required R
DS(ON)
for each MOSFET can now be calculated:
P-Ch R
DS(ON)
=
12(0.25)
5(2)
2
(1.27)
= 0.12
N-Ch R
DS(ON)
=
12(0.25)
7(2)
2
(1.27)
= 0.085
The P-channel requirement can be met by a Si9430DY,
while the N-channel requirement is exceeded by a
Si9410DY. Note that the most stringent requirement for
the N-channel MOSFET is with V
OUT
= 0 (i.e., short circuit).
During a continuous short circuit, the worst-case
N-channel dissipation rises to:
P
N
= I
SC(AVG)
2
(R
DS(ON)
)(1 + δ
N
)
With the 0.05 sense resistor I
SC(AVG)
= 2A will result,
increasing the 0.085 N-channel dissipation to 450mW at
a die temperature of 73°C.
C
IN
will require an RMS current rating of at least 1A at
temperature, and C
OUT
will require an ESR of 0.05 for
optimum efficiency.
Now allow V
IN
to drop to its minimum value. At lower input
voltages the operating frequency will decrease and the
P-channel will be conducting most of the time, causing its
power dissipation to increase. At V
IN(MIN)
= 7V:
f
MIN
= (1/2.92µs)[1 – (5V/7V)] = 98kHz
P
P
=
5V(0.12)(2A)
2
(1.27)
7V
= 435mW
This last step is necessary to assure that the power
dissipation and junction temperature of the P-channel are
not exceeded.
LTC1148 Adjustable Applications
When an output voltage other than 3.3V or 5V is required,
the LTC1148 adjustable version is used with an external
resistive divider from V
OUT
to V
FB
Pin 9 (see Figure 9). The
regulated voltage is determined by:
V
OUT
= 1.25
)
)
1 +
R2
R1
Figure 6. Suppression of Burst Mode Operation
R
SENSE
1000pF
R2
100
R1
100
R3
+
C
OUT
V
OUT
SENSE
+
(PIN 8)
SENSE
(PIN 7)
LTC1148 • F06
14
LTC1148
LTC1148-3.3/LTC1148-5
114835fd
APPLICATIO S I FOR ATIO
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With the addition of R3, a current is generated through R1
causing an offset of:
V
OFFSET
= V
OUT
)
)
R1
R1 + R3
If V
OFFSET
> 25mV, the minimum threshold will be can-
celled and Burst Mode
operation is prevented from occur-
ring. Since V
OFFSET
is constant, the maximum load current
is also decreased by the same offset. Thus, to get back to
the same I
MAX
, the value of the sense resistor must be
lower:
R
SENSE
75mV
I
MAX
To prevent noise spikes from erroneously tripping the
current comparator, a 1000pF capacitor is needed across
Pins 7 and 8.
Output Crowbar
An added feature to using an N-channel MOSFET as the
synchronous switch is the ability to crowbar the output
with the same MOSFET. Pulling the timing capacitor Pin
4 above 1.5V when the output voltage is greater than the
desired regulated value will turn “on” the N-channel
MOSFET.
A fault condition which causes the output voltage to go
above a maximum allowable value can be detected by
external circuitry. Turning on the N-channel MOSFET
when this fault is detected will cause large currents to flow
and blow the system fuse.
The N-channel MOSFET needs to be sized so it will safely
handle this overcurrent condition. The typical delay from
pulling the C
T
pin high and the N drive Pin 14 going high
is 250ns. Note: Under shutdown conditions, the N-chan-
nel is held OFF and pulling the C
T
pin high will not cause
the N-channel MOSFET to crowbar the output.
A simple N-channel FET can be used as an interface
between the overvoltage detect circuitry and the LTC1148
as shown in Figure 7.
Figure 7. Output Crowbar Interface
LTC1148
INTV
CC
C
T
VN2222LL
5
4
FROM CROWBAR DETECT CIRCUIT
(ACTIVE WHEN V
GATE
= V
IN
OFF WHEN V
GATE
= GROUND)
LTC1148 • F07
Troubleshooting Hints
Since efficiency is critical to LTC1148 series applications,
it is very important to verify that the circuit is functioning
correctly in both continuous and Burst Mode
operation.
The waveform to monitor is the voltage on the timing
capacitor Pin 4.
In continuous mode (I
LOAD
> I
BURST
) the voltage on the C
T
pin should be a sawtooth with a 0.9V
P-P
swing. This
voltage should never dip below 2V as shown in Figure 8a.
When load currents are low (I
LOAD
< I
BURST
) Burst Mode
operation should occur with the C
T
pin waveform periodi-
cally falling to ground as shown in Figure 8b.
3.3V
0V
(a) CONTINUOUS MODE OPERATION
3.3V
0V
(b) Burst Mode OPERATION
LTC1148 • F08
Figure 8. C
T
Waveforms
If Pin 4 is observed falling to ground at high output
currents, it indicates poor decoupling or improper ground-
ing. Refer to the Board Layout Checklist.
15
LTC1148
LTC1148-3.3/LTC1148-5
114835fd
Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1148 series. These items are also illustrated graphi-
cally in the layout diagram of Figure 9. Check the following
in your layout:
1. Are the signal and power grounds segregated? The
LTC1148 signal ground Pin 11 must return to the (–)
plate
of C
OUT
. The power ground returns to the
source of the N-channel MOSFET, anode of the
Schottky diode, and (–) plate of C
IN
, which should
have as short lead lengths as possible.
2. Does the LTC1148 SENSE
Pin 7 connect to a point
close to R
SENSE
and the (+) plate of C
OUT
? In adjust-
able applications, the resistive divider R1, R2 must be
connected between the (+) plate of C
OUT
and signal
ground.
3. Are the SENSE
and SENSE
+
leads routed together
with minimum PC trace spacing? The 1000pF capacitor
between Pins 7 and 8 should be as close as possible to
the LTC1148.
4. Does the (+) plate of C
IN
connect to the source of the
P-channel MOSFET as closely as possible? This capaci-
tor provides the AC current to the P-channel MOSFET.
5. Is the 1µF V
IN
decoupling capacitor connected closely
between Pin 3 and power ground Pin 12? This capacitor
carries the MOSFET driver peak currents.
6. Is the Shutdown Pin 10 actively pulled to ground during
normal operation? The Shutdown pin is high imped-
ance and must not be allowed to float.
Figure 9. LTC1148 Layout Diagram (See Board Layout Checklist)
APPLICATIO S I FOR ATIO
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1
2
3
4
5
6
7
14
13
12
11
10
9
8
C
OUT
1µF
D1
P-CHANNEL
1k
3300pF10nFC
T
LTC1148
R1
R2
+
R
SENSE
N-CHANNEL
+
C
IN
L
+
+
V
OUT
V
IN
OUTPUT DIVIDER REQUIRED WITH
ADJUSTABLE VERSION ONLY
BOLD LINES INDICATE HIGH CURRENT PATHS
LTC1148 • F09
SHUTDOWN
1000pF
P-DRIVE
V
IN
C
T
INTV
CC
I
TH
SENSE
N-DRIVE
PGND
SGND
SHDN
NC (V
FB
)
SENSE
+
NC NC
+

LTC1148CS#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Hi Eff Sync Buck Sw Regs
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