6.42
IDT70V9089/79S/L
High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges
11
Timing Waveform of a Bank Select Pipelined Read
(1,2)
t
SC
t
HC
CE
0(B1)
ADDRESS
(B1)
A
0
A
1
A
2
A
3
A
4
A
5
t
SA
t
HA
CLK
3750 drw 08
Q
0
Q
1
Q
3
DATA
OUT(B1)
t
CH2
t
CL2
t
CYC2
(3)
ADDRESS
(B2)
A
0
A
1
A
2
A
3
A
4
A
5
t
SA
t
HA
CE
0(B2)
DATA
OUT(B2)
Q
2
Q
4
t
CD2
t
CD2
t
CKHZ
t
CD2
t
CKLZ
t
DC
t
CKHZ
t
CD2
t
CKLZ
(3)
(3)
t
SC
t
HC
(3)
t
CKHZ
(3)
t
CKLZ
(3)
t
CD2
A
6
A
6
t
DC
t
SC
t
HC
t
SC
t
HC
NOTES:
1. B1 Represents Bank #1; B2 Represents Bank #2. Each Bank consists of one IDT70V9089/79 for this waveform,
and are setup for depth expansion in this example. ADDRESS
(B1) = ADDRESS(B2) in this situation.
2. OE and ADS = V
IL; CE1(B1), CE1(B2), R/W and CNTRST = VIH.
3. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
4. CE
0 and ADS = VIL; CE1 and CNTRST = VIH.
5. OE = V
IL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
6. If t
CCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD.
If t
CCS > maximum specified, then data from right port READ is not valid until tCCS + tCD1. tCWDD does not apply in this case.
Timing Waveform of a Bank Select Flow-Through Read
(6)
t
SC
t
HC
CE
0(B1)
ADDRESS
(B1)
A
0
A
1
A
2
A
3
A
4
A
5
t
SA
t
HA
CLK
3750 drw 08a
D
0
D
3
t
CD1
t
CKLZ
t
CKHZ
(1)
(1)
D
1
DATA
OUT(B1)
t
CH1
t
CL1
t
CYC1
(1)
ADDRESS
(B2)
A
0
A
1
A
2
A
3
A
4
A
5
t
SA
t
HA
CE
0(B2)
DATA
OUT(B2)
D
2
D
4
t
CD1
t
CD1
t
CKHZ
t
DC
t
CD1
t
CKLZ
t
SC
t
HC
(1)
t
CKHZ
(1)
t
CKLZ
(1)
t
CD1
A
6
A
6
t
DC
t
SC
t
HC
t
SC
t
HC
D
5
t
CD1
t
CKLZ
(1)
t
CKHZ
(1)
