LTC3556
12
3556f
PIN FUNCTIONS
SCL (Pin 13): Clock Input Pin for the I
2
C Serial Port. The
I
2
C logic levels are scaled with respect to DV
CC
.
SWCD3 (Pin 14): Switch Node for (Buck-Boost) Switch-
ing Regulator 3. Connected to internal power switches
C and D. External inductor connects between this node
and SWAB3.
PGOODALL (Pin 15): Logic Output. This in an open-drain
output which indicates that all enabled switching regula-
tors have settled to their final value. It can be used as a
power-on reset for the primary microprocessor.
SDA (Pin 16): Data Input Pin for the I
2
C Serial Port. The
I
2
C logic levels are scaled with respect to DV
CC
.
FB2 (Pin 17): Feedback Input for (Buck) Switching Regu-
lator 2. When regulator 2’s control loop is complete, this
pin servos to a fi xed voltage of 0.8V.
V
IN2
(Pin 18): Power Input for (Buck) Switching Regula-
tor 2. This pin will generally be connected to V
OUT
. A 1µF
MLCC capacitor is recommended on this pin.
SW2 (Pin 19): Power Transmission Pin for (Buck) Switch-
ing Regulator 2.
PROG (Pin 20): Charge Current Program and Charge
Current Monitor Pin. Connecting a resistor from PROG
to ground programs the charge current. If sufficient in-
put power is available in constant-current mode, this pin
servos to 1V. The voltage on this pin always represents
the actual charge current.
CHRG (Pin 21): Open-Drain Charge Status Output. The
CHRG pin indicates the status of the battery charger. Four
possible states are represented by CHRG: charging, not
charging, unresponsive battery and battery temperature
out of range. CHRG is modulated at 35kHz and switches
between a low and a high duty cycle for easy recogni-
tion by either humans or microprocessors. See Table 1.
CHRG requires a pull-up resistor and/or LED to provide
indication.
GATE (Pin 22): Analog Output. This pin controls the gate
of an optional external P-channel MOSFET transistor used
to supplement the ideal diode between V
OUT
and BAT. The
external ideal diode operates in parallel with the internal
ideal diode. The source of the P-channel MOSFET should
be connected to V
OUT
and the drain should be connected
to BAT. If the external ideal diode FET is not used, GATE
should be left floating.
BAT (Pin 23): Single Cell Li-Ion Battery Pin. Depending on
available V
BUS
power, a Li-Ion battery on BAT will either
deliver power to V
OUT
through the ideal diode or be charged
from V
OUT
via the battery charger.
V
OUT
(Pin 24): Output Voltage of the Switching Power-
Path Controller and Input Voltage of the Battery Charger.
The majority of the portable product should be powered
from V
OUT
. The LTC3556 will partition the available power
between the external load on V
OUT
and the internal battery
charger. Priority is given to the external load and any extra
power is used to charge the battery. An ideal diode from
BAT to V
OUT
ensures that V
OUT
is powered even if the load
exceeds the allotted power from V
BUS
or if the V
BUS
power
source is removed. V
OUT
should be bypassed with a low
impedance ceramic capacitor.
V
BUS
(Pin 25): Primary Input Power Pin. This pin delivers
power to V
OUT
via the SW pin by drawing controlled current
from a DC source such as a USB port or wall adapter.
SW (Pin 26): Power Transmission Pin for the USB Power
Path. The SW pin delivers power from V
BUS
to V
OUT
via the
step-down switching regulator. A 3.3µH inductor should
be connected from SW to V
OUT
.
SEQ (Pin 27): Sequence Select Logic Input. Three-state
input which determines start-up sequence after ENALL
is asserted.
If tied to GND, start-up sequence is:
Buck 1 → Buck 2 → Buck-Boost
If tied to V
OUT
, start-up sequence is:
Buck 1 → Buck-Boost → Buck 2
If left fl oating, start-up sequence is:
Buck-Boost → Buck 1 → Buck 2
ENALL (Pin 28): Enable All Logic Input. Enables all three
switching regulators in sequence according to the state of
the SEQ pin. Active high. Has a 5.5M internal pull-down
resistor. Alternately, all switching regulators can be indi-
vidually enabled via the I
2
C serial port.
Exposed Pad (Pin 29): Ground. The Exposed Pad should
be connected to a continuous ground plane on the second
layer of the printed circuit board by several vias directly
under the LTC3556.
