LTC3556EUFD#PBF Datasheet LTC3556EUFD#PBF, LTC3556EUFD#TRPBF | P19-P21

LTC3556

3556f

have approximately 3°C of hysteresis to prevent oscillation

about the trip point. Grounding the NTC pin disables the

NTC charge pausing function.

Thermal Regulation

To optimize charging time, an internal thermal feedback

loop may automatically decrease the programmed charge

current. This will occur if the die temperature rises to

approximately 110°C. Thermal regulation protects the

LTC3556 from excessive temperature due to high power

operation or high ambient thermal conditions and allows

the user to push the limits of the power handling capability

with a given circuit board design without risk of damag-

ing the LTC3556 or external components. The beneﬁt

of the LTC3556 thermal regulation loop is that charge

current can be set according to actual conditions rather

than worst-case conditions with the assurance that the

battery charger will automatically reduce the current in

worst-case conditions.

C Interface

The LTC3556 may receive commands from a host (mas-

ter) using the standard I

C 2-wire interface. The Timing

Diagram shows the timing relationship of the signals on

the bus. The two bus lines, SDA and SCL, must be high

when the bus is not in use. External pull-up resistors or

current sources, such as the LTC1694 I

C accelerator, are

required on these lines. The LTC3556 is a receive-only

(slave) device. The I

C control signals, SDA and SCL are

scaled internally to the DV

supply. DV

should be con-

nected to the same power supply as the microcontroller

generating the I

C signals.

The I

C port has an undervoltage lockout on the DV

pin. When DV

is below approximately 1V, the I

C serial

port is cleared and switching regulators 1 and 3 are set

to full scale.

Bus Speed

The I

C port is designed to be operated at speeds of up

to 400kHz. It has built-in timing delays to ensure correct

operation when addressed from an I

C compliant master

device. It also contains input ﬁlters designed to suppress

glitches should the bus become corrupted.

Start and Stop Condition

A bus master signals the beginning of a communication

to a slave device by transmitting a Start condition. A Start

condition is generated by transitioning SDA from high

to low while SCL is high. When the master has ﬁnished

communicating with the slave, it issues a Stop condition

by transitioning SDA from low to high while SCL is high.

The bus is then free for communication with another I

device.

Byte Format

Each byte sent to the LTC3556 must be eight bits long

followed by an extra clock cycle for the Acknowledge bit

to be returned by the LTC3556. The data should be sent

to the LTC3556 most signiﬁcant bit (MSb) ﬁrst.

Acknowledge

The Acknowledge signal is used for handshaking between

the master and the slave. An Acknowledge (active low)

generated by the slave (LTC3556) lets the master know

that the latest byte of information was received. The

Acknowledge related clock pulse is generated by the

master. The master releases the SDA line (high) during

the Acknowledge clock cycle. The slave receiver must pull

down the SDA line during the Acknowledge clock pulse

so that it remains a stable Low during the High period of

this clock pulse.

Slave Address

The LTC3556 responds to only one 7-bit address which

has been factory programmed to 0001001. The LSb of the

address byte is 1 for Read and 0 for Write. This device is

write only corresponding to an address byte of 00010010

(0×12). If the correct seven bit address is given but the

R/W bit is 1, the LTC3556 will not respond.

OPERATION

LTC3556

3556f

Bus Write Operation

The master initiates communication with the LTC3556

with a Start condition and a 7-bit address followed by

the Write Bit R/W = 0. If the address matches that of the

LTC3556, the LTC3556 returns an Acknowledge. The master

should then deliver the most signiﬁcant data byte. Again

the LTC3556 acknowledges and the cycle is repeated for

a total of one address byte and two data bytes. Each data

byte is transferred to an internal holding latch upon the

return of an Acknowledge. After both data bytes have been

transferred to the LTC3556, the master may terminate the

communication with a Stop condition. Alternatively, a

Repeat-Start condition can be initiated by the master and

another chip on the I

C bus can be addressed. This cycle

can continue indeﬁnitely and the LTC3556 will remember

the last input of valid data that it received. Once all chips on

the bus have been addressed and sent valid data, a global

Stop condition can be sent and the LTC3556 will update its

command latch with the data that it had received.

In certain circumstances the data on the I

C bus may

become corrupted. In these cases the LTC3556 responds

appropriately by preserving only the last set of complete

data that it has received. For example, assume the LTC3556

has been successfully addressed and is receiving data

when a Stop condition mistakenly occurs. The LTC3556

will ignore this stop condition and will not respond until

a new Start condition, correct address, new set of data

and Stop condition are transmitted.

Likewise, with only one exception, if the LTC3556 was

previously addressed and sent valid data but not updated

with a Stop, it will respond to any Stop that appears on

the bus, independent of the number of Repeat-Starts that

have occurred. If a Repeat-Start is given and the LTC3556

successfully acknowledges its address and ﬁ rst byte, it

will not respond to a Stop until both bytes of the new data

have been received and acknowledged.

OPERATION

Table 2. I

C Serial Port Mapping (Defaults to 0xFF00 in Reset State or if DV

= 0V)

A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0

Switching Regulator 1

Voltage (See Table 4)

Switching Regulator 3

Voltage (See Table 4)

Disable

Battery

Charger

Switching Regulator

Modes (See Table 5)

Enable

Regulator

Enable

Regulator

Enable

Regulator

Input Current Limit

(See Table 3)

Table 3. USB Current Limit Settings

B1 B0 USB SETTING

0 1 10x Mode (Wall 1A Limit)

1 1 5x Mode (USB 500mA Limit)

0 0 1x Mode (USB 100mA Limit)

1 0 Suspend

Table 4. Switching Regulator Servo Voltage

A7 A6 A5 A4 SWITCHING REGULATOR 1 SERVO VOLTAGE

A3 A2 A1 A0 SWITCHING REGULATOR 3 SERVO VOLTAGE

0000 0.425V

0001 0.450V

0010 0.475V

0011 0.500V

0100 0.525V

0101 0.550V

0110 0.575V

0111 0.600V

1000 0.625V

1001 0.650V

1010 0.675V

1011 0.700V

1100 0.725V

1101 0.750V

1110 0.775V

1111 0.800V

Table 5. Switching Regulator Modes

B6 B5

MODE OF (BUCK) SWITCHING

REGULATORS 1 AND 2

MODE OF (BUCK-BOOST)

SWITCHING REGULATOR 3

0 0 Pulse Skip Mode PWM Mode

1 1 Burst Mode Operation

0 1 Forced Burst Mode Operation Burst Mode Operation

1 0 LDO Mode

LTC3556

3556f

Disabling the I

C Port

The I

C serial port can be disabled by grounding the

pin. In this mode, control automatically passes to

the individual logic input pins ENALL and SEQ. However,

considerable functionality is not available in this mode such

as the ability to independently enable the three switching

regulators and disable the battery charger. In addition,

with the I

C port disabled, both programmable switching

regulators default to a ﬁxed servo voltage of 0.8V, both

400mA bucks default to pulse skip mode, the 1A buck-

boost defaults to PWM mode, and the USB input current

limit defaults to 1x mode (100mA Limit).

PGOODALL Pin

The PGOODALL pin is an open-drain output used to in-

dicate that all enabled switching regulators have reached

their ﬁnal voltage. PGOODALL remains low impedance

until the last enabled regulator in the sequence reaches

92% of its regulation value. A 230ms delay is included

to allow a system microcontroller ample time to reset

itself. PGOODALL may be used as a power-on reset to the

microprocessor powered by one (or more) of the three

regulated outputs. PGOODALL is an open-drain output

and requires a pull-up resistor to the input voltage of

the monitoring microprocessor or another appropriate

power source.

400mA Step-Down Switching Regulators

The LTC3556 contains two 2.25MHz step-down (buck)

constant-frequency current mode switching regulators.

Each buck regulator can provide up to 400mA of output

current. Both buck regulators can be programmed for a

minimum output voltage of 0.8V and can be used to power

a microcontroller core, microcontroller I/O, memory, disk

drive or other logic circuitry. One of the buck regulators

has I

C programmable set-points for on-the-ﬂy power

savings. Both buck converters support 100% duty cycle

operation (low dropout mode) when their input voltage

drops very close to their output voltage. To suit a variety

of applications, selectable mode functions can be used to

trade off noise for efﬁciency. Four modes are available to

control the operation of the LTC3556’s buck regulators.

At moderate to heavy loads, the pulse skip mode provides

the least noise switching solution. At lighter loads, either

Burst Mode operation, forced Burst Mode operation or

LDO mode may be selected. The buck regulators include

soft-start to limit inrush current when powering on, short-

circuit current protection and switch node slew limiting

circuitry to reduce radiated EMI. No external compensation

components are required. The operating mode of the buck

regulators can be set by I

C control and defaults to pulse

skip mode if the I

C port is not used. Both buck converters

are enabled (along with the buck-boost) when the ENALL

pin is asserted or each may be individually enabled by the

C port. Buck regulator 1 has a programmable feedback

servo voltage via I

C control (which defaults to 800mV if

the I

C port is not used) whereas buck regulator 2 has a

ﬁ xed feedback servo voltage of 800mV. The buck regulator

input supplies V

IN1

and V

IN2

will generally be connected

to the system load pin V

OUT

Buck Regulator Output Voltage Programming

Both buck regulators can be programmed for output

voltages greater than 0.8V. The full-scale output voltage

for each buck regulator is programmed using a resistor

divider from the buck regulator output connected to the

feedback pins (FB1 and FB2) such that:

OUTX FBX

⎛

⎝

⎜

⎞

⎠

⎟

where V

FBX

ranges from 0.425V to 0.8V for buck regula-

tor 1 and V

FBX

is ﬁxed at 0.8V for buck regulator 2. See

Figure 4.

Typical values for R1 are in the range of 40k to 1M. The

capacitor, C

, cancels the pole created by feedback resis-

tors and the input capacitance of the FBx pin and also helps

to improve transient response for output voltages much

OPERATION

INx

LTC3556

SWx

R1 C

OUT

OUTx

3556 F04

FBx

GND

Figure 4. Buck Converter Application Circuit

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LTC3556EUFD#PBF

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Battery Management High Efficiency USB Pwr Mgr + B/B + Dual Buck DC/DC

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