LTC3556
28
3556f
Closing the Feedback Loop
The LTC3556 incorporates voltage mode PWM control. The
control to output gain varies with operation region (buck,
boost, buck-boost), but is usually no greater than 20. The
output fi lter exhibits a double-pole response given by:
f
LC
Hz
FILTER POLE
OUT
_
••
=
1
2 π
where C
OUT
is the output fi lter capacitor.
The output fi lter zero is given by:
f
RC
Hz
FILTER ZERO
ESR OUT
_
••
=
1
2 π
where R
ESR
is the capacitor equivalent series resistance.
A troublesome feature in boost mode is the right-half plane
zero (RHP), and is given by:
f
V
ILV
Hz
RHPZ
IN
OUT OUT
=
2
2• π
The loop gain is typically rolled off before the RHP zero
frequency.
A simple Type I compensation network (as shown in
Figure 5) can be incorporated to stabilize the loop but
at the cost of reduced bandwidth and slower transient
response. To ensure proper phase margin, the loop must
cross unity-gain a decade before the LC double pole.
The unity-gain frequency of the error amplifi er with the
Type I compensation is given by:
f
RCP
Hz
UG
=
1
211•• π
Most applications demand an improved transient response
to allow a smaller output fi lter capacitor. To achieve a higher
bandwidth, Type III compensation is required. Two zeros
are required to compensate for the double-pole response.
Type III compensation also reduces any V
OUT3
overshoot
at start-up.
The compensation network depicted in Figure 6 yields the
transfer function:
V
VRCC
sR C s R R C
C
OUT
3
3
1
11 2
1221 133
=
+
+++
()
()[()]
sssRCC sRC1212133+
+(|| )( )
A Type III compensation network attempts to introduce
a phase bump at a higher frequency than the LC double
pole. This allows the system to cross unity gain after the
LC double pole, and achieve a higher bandwidth. While
attempting to cross over after the LC double pole, the
system must still cross over before the boost right-half
plane zero. If unity gain is not reached suffi ciently before
the right-half plane zero, then the –180° of phase lag from
APPLICATIONS INFORMATION
7
+
ERROR
AMP
0.8V
R1
R2
3556 F05
FB3
8
V
C3
C
P1
V
OUT3
Figure 5. Error Amplifi er with Type I Compensation
7
+
ERROR
AMP
0.8V
R1
R3
C3
R
FB
3556 F06
FB3
8
V
C3
C2
C1
R2
V
OUT3
Figure 6. Error Amplifi er with Type III Compensation
LTC3556
29
3556f
the LC double pole combined with the –90° of phase lag
from the right-half plane zero will result in negating the
phase bump of the compensator.
The compensator zeros should be placed either before
or only slightly after the LC double pole such that their
positive phase contributions offset the –180° that occurs
at the fi lter double pole. If they are placed at too low of a
frequency, they will introduce too much gain to the system
and the crossover frequency will be too high. The two high
frequency poles should be placed such that the system
crosses unity gain during the phase bump introduced
by the zeros and before the boost right-half plane zero
and such that the compensator bandwidth is less than
the bandwidth of the error amp (typically 900kHz). If the
gain of the compensation network is ever greater than
the gain of the error amplifi er, then the error amplifi er no
longer acts as an ideal op amp, and another pole will be
introduced at the same point.
Recommended Type III compensation components for a
3.3V output:
R1: 324kΩ
R
FB
: 105kΩ
C1: 10pF
R2: 15kΩ
C2: 330pF
R3: 121k
C3: 33pF
C
OUT
: 22µF
L
OUT
: 2.2µH
Over-Programming the Battery Charger
The USB high power specification allows for up to 2.5W to
be drawn from the USB port (5V × 500mA). The PowerPath
switching regulator transforms the voltage at V
BUS
to just
above the voltage at BAT with high efficiency, while limiting
power to less than the amount programmed at CLPROG.
In some cases the battery charger may be programmed
(with the PROG pin) to deliver the maximum safe charging
current without regard to the USB specifications. If there
is insufficient current available to charge the battery at the
programmed rate, the PowerPath regulator will reduce
charge current until the system load on V
OUT
is satisfied
and the V
BUS
current limit is satisfied. Programming the
battery charger for more current than is available will
not cause the average input current limit to be violated.
It will merely allow the battery charger to make use of
all available power to charge the battery as quickly as
possible, and with minimal power dissipation within the
battery charger.
Alternate NTC Thermistors and Biasing
The LTC3556 provides temperature qualified charging if
a grounded thermistor and a bias resistor are connected
to NTC. By using a bias resistor whose value is equal to
the room temperature resistance of the thermistor (R25)
the upper and lower temperatures are pre-programmed
to approximately 40°C and 0°C, respectively (assuming
a Vishay “Curve 1” thermistor).
The upper and lower temperature thresholds can be ad-
justed by either a modification of the bias resistor value
or by adding a second adjustment resistor to the circuit.
If only the bias resistor is adjusted, then either the upper
or the lower threshold can be modified but not both. The
other trip point will be determined by the characteristics
of the thermistor. Using the bias resistor in addition to an
adjustment resistor, both the upper and the lower tempera-
ture trip points can be independently programmed with
the constraint that the difference between the upper and
lower temperature thresholds cannot decrease. Examples
of each technique follow.
NTC thermistors have temperature characteristics which
are indicated on resistance-temperature conversion tables.
The Vishay-Dale thermistor NTHS0603N011-N1003F, used
APPLICATIONS INFORMATION
LTC3556
30
3556f
in the following examples, has a nominal value of 100k
and follows the Vishay “Curve 1” resistance-temperature
characteristic.
In the explanation below, the following notation is used.
R25 = Value of the thermistor at 25°C
R
NTC|COLD
= Value of thermistor at the cold trip point
R
NTC|HOT
= Value of thermistor at the hot trip point
r
COLD
= Ratio of R
NTC|COLD
to R25
r
HOT
= Ratio of R
NTC|COLD
to R25
R
NOM
= Primary thermistor bias resistor (see Figure 7a)
R1 = Optional temperature range adjustment resistor
(see Figure 7b)
The trip points for the LTC3556’s temperature qualification
are internally programmed at 0.349 • V
BUS
for the hot
threshold and 0.765 • V
BUS
for the cold threshold.
Therefore, the hot trip point is set when:
R
RR
VV
NTCHOT
NOM NTCHOT
BUS BUS
|
|
•.
+
= 0 349
and the cold trip point is set when:
R
RR
VV
NTCCOLD
NOM NTCCOLD
BUS BUS
|
|
•.
+
= 0 765
Solving these equations for R
NTC|COLD
and R
NTC|HOT
results
in the following:
R
NTC|HOT
= 0.536 • R
NOM
and
R
NTC|COLD
= 3.25 • R
NOM
By setting R
NOM
equal to R25, the above equations result
in r
HOT
= 0.536 and r
COLD
= 3.25. Referencing these ratios
to the Vishay Resistance-Temperature Curve 1 chart gives
a hot trip point of about 40°C and a cold trip point of about
0°C. The difference between the hot and cold trip points
is approximately 40°C.
By using a bias resistor, R
NOM
, different in value from
R25, the hot and cold trip points can be moved in either
direction. The temperature span will change somewhat due
APPLICATIONS INFORMATION
to the nonlinear behavior of the thermistor. The following
equations can be used to easily calculate a new value for
the bias resistor:
R
r
R
R
r
R
NOM
HOT
NOM
COLD
=
=
0 536
25
325
25
.
.
where r
HOT
and r
COLD
are the resistance ratios at the de-
sired hot and cold trip points. Note that these equations
are linked. Therefore, only one of the two trip points can
be chosen, the other is determined by the default ratios
designed in the IC. Consider an example where a 60°C
hot trip point is desired.
From the Vishay Curve 1 R-T characteristics, r
HOT
is 0.2488
at 60°C. Using the above equation, R
NOM
should be set
to 46.4k. With this value of R
NOM
, the cold trip point is
about 16°C. Notice that the span is now 44°C rather than
the previous 40°C. This is due to the decrease in “tem-
perature gain” of the thermistor as absolute temperature
increases.
The upper and lower temperature trip points can be inde-
pendently programmed by using an additional bias resistor
as shown in Figure 7b. The following formulas can be used
to compute the values of R
NOM
and R1:
R
rr
R
RRr
NOM
COLD HOT
NOM HOT
=
=
.
.•
2 714
25
1 0 536 RR25
For example, to set the trip points to 0°C and 45°C with
a Vishay Curve 1 thermistor choose:
Rkk
NOM
==
3 266 0 4368
2 714
100 104 2
.–.
.
•.
The nearest 1% value is 105k.
R1 = 0.536 • 105k – 0.4368 • 100k = 12.6k
The nearest 1% value is 12.7k. The final solution is shown
in Figure 7b and results in an upper trip point of 45°C and
a lower trip point of 0°C.

LTC3556EUFD#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Battery Management High Efficiency USB Pwr Mgr + B/B + Dual Buck DC/DC
Lifecycle:
New from this manufacturer.
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